Patents by Inventor Katsuyoshi Washio

Katsuyoshi Washio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190140151
    Abstract: A light emitting device includes: first and second conductive members disposed on an upper surface of a substrate; and a light emitting element disposed above a portion of an upper surface of a first electrode layer and a portion of an upper surface of a second electrode layer, above the spacer region. The upper surface of the first electrode layer and the upper surface of the second electrode layer above spacer region are located lower than the upper surface of the first electrode layer above the first conductive member and the upper surface of the second electrode layer above the second conductive member, and a reflectance of the first conductive member and the second to light emitted from the light emitting element is higher than reflectance of the first electrode layer and the second electrode layer to light emitted from the light emitting element.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 9, 2019
    Applicant: NICHIA CORPORATION
    Inventors: Katsuyoshi KADAN, Hajime WASHIO
  • Patent number: 8711523
    Abstract: A magnetoresistance device comprises a substrate, an elongate semiconductor channel extending in a first direction and at least two conductive leads providing a set of contacts to the channel. The device may comprise an optional semiconductor shunt in contact with the channel. The optional shunt, channel and set of contacts are stacked relative to the substrate in a second direction which is perpendicular to the first direction and the surface of the substrate. The device has a side face running along the channel. The device is responsive to a magnetic field generally perpendicular to the side face.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: April 29, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Ogawa, David Williams, Hiroshi Fukuda, Katsuyoshi Washio
  • Patent number: 8212615
    Abstract: There is disclosed a variable-gain amplifier circuit that operates on a low voltage, exhibits low distortion, provides a wide range of variation, and is suitable for use in a low-power-consumption wireless communication system. The variable-gain amplifier circuit is configured so that a variable-load circuit, which includes three reactance function elements and provides a wide range of impedance variation, is connected to a conductor circuit whose output terminal generates a positive-phase output current proportional to conductance with respect to an input voltage.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: July 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Toru Masuda, Nobuhiro Shiramizu, Takahiro Nakamura, Katsuyoshi Washio
  • Patent number: 8121579
    Abstract: The present invention provides a semiconductor integrated circuit including an active mixer circuit that is operated at low voltage, low noise, and low power consumption. It includes a transconductance amplifier, a transformer, and a multiplier, connects a transformer between the transconductance amplifier and the multiplier, and separates between the transconductance amplifier and the multiplier with respect to direct current inside the transformer. Further, each of the tranconductance amplifier and the multiplier is configured of transistors that are single-stacked between the supply voltage terminal and ground terminal.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: February 21, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Nobuhiro Shiramizu, Toru Masuda, Takahiro Nakamura, Katsuyoshi Washio, Masamichi Tanabe
  • Publication number: 20110102947
    Abstract: A magnetoresistance device comprises a substrate, an elongate semiconductor channel extending in a first direction and at least two conductive leads providing a set of contacts to the channel. The device may comprise an optional semiconductor shunt in contact with the channel. The optional shunt, channel and set of contacts are stacked relative to the substrate in a second direction which is perpendicular to the first direction and the surface of the substrate. The device has a side face running along the channel. The device is responsive to a magnetic field generally perpendicular to the side face.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 5, 2011
    Inventors: Susumu OGAWA, David Williams, Hiroshi Fukuda, Katsuyoshi Washio
  • Patent number: 7842973
    Abstract: A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier gene
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: November 30, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
  • Publication number: 20100271122
    Abstract: There is disclosed a variable-gain amplifier circuit that operates on a low voltage, exhibits low distortion, provides a wide range of variation, and is suitable for use in a low-power-consumption wireless communication system. The variable-gain amplifier circuit is configured so that a variable-load circuit, which includes three reactance function elements and provides a wide range of impedance variation, is connected to a conductor circuit whose output terminal generates a positive-phase output current proportional to conductance with respect to an input voltage.
    Type: Application
    Filed: April 22, 2010
    Publication date: October 28, 2010
    Inventors: Toru MASUDA, Nobuhiro Shiramizu, Takahiro Nakamura, Katsuyoshi Washio
  • Publication number: 20090221259
    Abstract: The present invention provides a semiconductor integrated circuit including an active mixer circuit that is operated at low voltage, low noise, and low power consumption. It includes a transconductance amplifier, a transformer, and a multiplier, connects a transformer between the transconductance amplifier and the multiplier, and separates between the transconductance amplifier and the multiplier with respect to direct current inside the transformer. Further, each of the tranconductance amplifier and the multiplier is configured of transistors that are single-stacked between the supply voltage terminal and ground terminal.
    Type: Application
    Filed: February 12, 2009
    Publication date: September 3, 2009
    Inventors: Nobuhiro SHIRAMIZU, Toru Masuda, Takahiro Nakamura, Katsuyoshi Washio, Masamichi Tanabe
  • Patent number: 7521734
    Abstract: A bipolar transistor is provided in which both the base resistance and the base-collector capacitance are reduced and which is capable of operating at a high cutoff frequency. The semiconductor device is structured so that the emitter and extrinsic base are separated from each other by an insulator sidewall and the bottom faces of the insulator sidewall, and the emitter are approximately on the same plane. The extrinsic base electrode and the collector region are separated from each other by an insulator.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: April 21, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Eiji Oue, Katsuyoshi Washio, Hiromi Shimamoto, Katsuya Oda, Makoto Miura
  • Patent number: 7368763
    Abstract: A high quality silicon carbide (SiC) layer being substantially lower in threading dislocation density than a prior layer is formed on silicon (Si) substrate. A semiconductor device is fabricated in such a way that a semiconductor buffer layer containing Si in part and being higher in defect density than a Si substrate is formed on the Si substrate on the upper portion of which are formed a plurality of pairs of facets being mirror-symmetrical to the surface orientation of a semiconductor substrate, further on the top of the layer a SiC layer is sequentially formed.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: May 6, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Miura, Katsuya Oda, Katsuyoshi Washio
  • Patent number: 7214973
    Abstract: A bipolar type semiconductor device capable of attaining high current gain and high cut-off frequency and performing a satisfactory transistor operation also in a high current region while maintaining a high breakdown voltage performance, as well as a method of manufacturing the semiconductor device, are provided. In a collector comprising a first semiconductor layer and a second semiconductor layer narrower in band gap than the first semiconductor layer, an impurity is doped so as to have a peak of impurity concentration within the second collector layer and so that the value of the peak is higher than the impurity concentration at any position within the first collector layer. It is preferable to adjust the concentration of the doped impurity in such a manner that a collector-base depletion layer extends up to the first collector layer.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: May 8, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
  • Publication number: 20070045664
    Abstract: A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier gene
    Type: Application
    Filed: July 13, 2006
    Publication date: March 1, 2007
    Inventors: Markoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
  • Patent number: 7098740
    Abstract: There is provided not only a radio frequency power amplifier using an SiGe HBT subject to a little amplification distortion, but also a communication system using the same. A conventional radio frequency power amplifier provides base bias paths of transistors Q1 through QN (SiGe HBT) with bias resistors R11 through R1N having resistance values three to five times higher than those of a ballast resistor attached to each transistor's base. A coil LB is provided in parallel with the bias resistor as a means for compensating a voltage drop due to direct current component IDC flowing through the bias resistor. Addition of the bias resistor suppresses non-linearity of low-frequency variations in an output current. Addition of the coil compensates for voltage drop. Accordingly, the maximum linear output power can be improved. As a result, it is possible to provide the power amplifier subject to a little amplification distortion within a wide output range.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: August 29, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Masao Kondo, Toru Masuda, Katsuyoshi Washio
  • Patent number: 7095043
    Abstract: An (SiGe)C layer having a stoichiometric ratio of about 1:1 is locally formed on an Si layer, a large forbidden band width semiconductor device is prepared inside the layered structure thereof and an Si semiconductor integrated circuit is formed in the regions not formed with the layered structure, whereby high frequency high power operation of the device is enabled by the large forbidden band width semiconductor device and high performance is attained by hybridization of the Si integrated circuit.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: August 22, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Oda, Nobuyuki Sugii, Makoto Miura, Isao Suzumura, Katsuyoshi Washio
  • Publication number: 20060169987
    Abstract: A high quality silicon carbide (SiC) layer being substantially lower in threading dislocation density than a prior layer is formed on silicon (Si) substrate. A semiconductor device is fabricated in such a way that a semiconductor buffer layer containing Si in part and being higher in defect density than a Si substrate is formed on the Si substrate on the upper portion of which are formed a plurality of pairs of facets being mirror-symmetrical to the surface orientation of a semiconductor substrate, further on the top of the layer a SiC layer is sequentially formed.
    Type: Application
    Filed: March 7, 2005
    Publication date: August 3, 2006
    Inventors: Makoto Miura, Katsuya Oda, Katsuyoshi Washio
  • Patent number: 7071500
    Abstract: A bipolar semiconductor device including a collector layer covered at a portion of an outer periphery thereof with an insulating film and having a shape extending in an upper direction and a horizontal direction, with a gap being formed between the collector layer and the insulating film, and further including a base layer and an emitter layer disposed over the collector layer, and a manufacturing method of the semiconductor device. Since the collector layer has a shape extending in a portion thereof in the upward direction and the horizontal direction, an external collector region can be deleted, and both the parasitic capacitance and the collector capacitance in the intrinsic portion attributable to the collector can be decreased and, accordingly, a bipolar transistor capable of high speed operation at a reduced consumption power can be constituted.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: July 4, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Makoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
  • Patent number: 7045412
    Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: May 16, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Nobuyuki Sugii, Masatoshi Morikawa, Isao Yoshida, Katsuyoshi Washio
  • Publication number: 20060043418
    Abstract: A bipolar type semiconductor device capable of attaining high current gain and high cut-off frequency and performing a satisfactory transistor operation also in a high current region while maintaining a high breakdown voltage performance, as well as a method of manufacturing the semiconductor device, are provided. In a collector comprising a first semiconductor layer and a second semiconductor layer narrower in band gap than the first semiconductor layer, an impurity is doped so as to have a peak of impurity concentration within the second collector layer and so that the value of the peak is higher than the impurity concentration at any position within the first collector layer. It is preferable to adjust the concentration of the doped impurity in such a manner that a collector-base depletion layer extends up to the first collector layer.
    Type: Application
    Filed: March 3, 2005
    Publication date: March 2, 2006
    Inventors: Makoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
  • Patent number: 6995054
    Abstract: A semiconductor device having an MODFET and at least one other device formed on one identical semiconductor substrate, in which an intrinsic region for the MODFET is formed by selective growth in a groove formed on a semiconductor substrate having an insulation film on the side wall of the groove, and single-crystal silicon at the bottom of the groove, is disclosed. The step between the MODFET and the at least one other device mounted together on one identical substrate can be thereby decreased, and each of the devices can be reduced in the size and integrated to a high degree, and the interconnection length can be shortened to reduce power consumption.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: February 7, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Katsuya Oda, Katsuyoshi Washio
  • Patent number: 6987983
    Abstract: The purpose of this invention is to realize a radio frequency monolithic integrated circuit high in performance, small in size and low in cost, where transistors and passive elements are arranged on a chip in which a conductive silicon substrate functions as a ground. Since the electromagnetic fields of passive elements induce a current in a conductive silicon substrate, a loss due to generation of Joule heat or the like occurs to lead to deterioration of the performance of the passive elements. To solve this problem, an SOI layer comprising a semiconductor layer having a large thickness and a high resistivity and a conductive silicon substrate is used, and passive elements and an active element are formed on the same substrate. Alternatively, a cavity is provided in the conductive substrate directly beneath the SOI layer in the region where the passive elements are formed, thereby attaining the object.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: January 17, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Masao Kondo, Katsuyoshi Washio, Masatada Horiuchi