Patents by Inventor Katsuyoshi Washio
Katsuyoshi Washio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6956255Abstract: A high-speed bipolar transistor is provided which is improved in the effect of heat radiation without increasing the substrate capacitance. The heat radiation connection between a base region and a silicon substrate includes a p+ extrinsic base polysilicon electrode and a polysilicon layer buried in an isolation groove with a very thin silicon dioxide side wall. Accordingly, the heat generated at the base is radiated through this path to the silicon substrate. Further, the film thickness of the silicon dioxide on the inner wall of the isolation groove is sufficiently increased compared with previous structures to prevent an increase in the substrate capacitance. Consequently, there can be obtained a bipolar transistor which operates at high speed, and is improved in the effect of heat radiation without increasing the substrate capacitance.Type: GrantFiled: November 7, 2002Date of Patent: October 18, 2005Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.Inventors: Eiji Oue, Katsuyoshi Washio, Masao Kondo, Hiromi Shimamoto
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Patent number: 6936875Abstract: With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.Type: GrantFiled: September 30, 2003Date of Patent: August 30, 2005Assignee: Renesas Technology Corp.Inventors: Nobuyuki Sugii, Kazuhiro Ohnishi, Katsuyoshi Washio
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Publication number: 20050001238Abstract: A bipolar transistor is provided in which both the base resistance and the base-collector capacitance are reduced and which is capable of operating at a high cutoff frequency. The semiconductor device is structured so that the emitter and extrinsic base are separated from each other by an insulator sidewall and the bottom faces of the insulator sidewall, and the emitter are approximately on the same plane. The extrinsic base electrode and the collector region are separated from each other by an insulator.Type: ApplicationFiled: May 28, 2004Publication date: January 6, 2005Inventors: Eiji Oue, Katsuyoshi Washio, Hiromi Shimamoto, Katsuya Oda, Makoto Miura
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Publication number: 20050003573Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.Type: ApplicationFiled: July 26, 2004Publication date: January 6, 2005Inventors: Nobuyuki Sugii, Masatoshi Morikawa, Isao Yoshida, Katsuyoshi Washio
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Publication number: 20040262715Abstract: A bipolar semiconductor device including a collector layer covered at a portion of an outer periphery thereof with an insulating film and having a shape extending in an upper direction and a horizontal direction, with a gap being formed between the collector layer and the insulating film, and further including a base layer and an emitter layer disposed over the collector layer, and a manufacturing method of the semiconductor device. Since the collector layer has a shape extending in a portion thereof in the upward direction and the horizontal direction, an external collector region can be deleted, and both the parasitic capacitance and the collector capacitance in the intrinsic portion attributable to the collector can be decreased and, accordingly, a bipolar transistor capable of high speed operation at a reduced consumption power can be constituted.Type: ApplicationFiled: June 15, 2004Publication date: December 30, 2004Inventors: Makoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
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Publication number: 20040256613Abstract: An (SiGe)C layer having a stoichiometric ratio of about 1:1 is locally formed on an Si layer, a large forbidden band width semiconductor device is prepared inside the layered structure thereof and an Si semiconductor integrated circuit is formed in the regions not formed with the layered structure, whereby high frequency high power operation of the device is enabled by the large forbidden band width semiconductor device and high performance is attained by hybridization of the Si integrated circuit.Type: ApplicationFiled: March 2, 2004Publication date: December 23, 2004Inventors: Katsuya Oda, Nobuyuki Sugii, Makoto Miura, Isao Suzumura, Katsuyoshi Washio
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Patent number: 6815707Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.Type: GrantFiled: September 30, 2002Date of Patent: November 9, 2004Assignee: Renesas Technology Corp.Inventors: Nobuyuki Sugii, Masatoshi Morikawa, Isao Yoshida, Katsuyoshi Washio
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Patent number: 6815822Abstract: Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.Type: GrantFiled: September 10, 2002Date of Patent: November 9, 2004Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Masao Kondo, Katsuyoshi Washio, Eiji Oue, Hiromi Shimamoto
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Publication number: 20040213580Abstract: The present invention provides an optical transmitter using a multiplexer which can maintain a timing margin between a clock and data as an operating reference at an optimal value when data transmission speed, or data rate to be handled is changed.Type: ApplicationFiled: November 21, 2002Publication date: October 28, 2004Applicants: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Toru Masuda, Kenichi Ohhata, Nobuhiro Shiramizu, Eiji Ohue, Katsuyoshi Washio
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Publication number: 20040198253Abstract: The purpose of this invention is to realize a radio frequency monolithic integrated circuit high in performance, small in size and low in cost, where transistors and passive elements are arranged on a chip in which a conductive silicon substrate functions as a ground. Since the electromagnetic fields of passive elements induce a current in a conductive silicon substrate, a loss due to generation of Joule heat or the like occurs to lead to deterioration of the performance of the passive elements. To solve this problem, an SOI layer comprising a semiconductor layer having a large thickness and a high resistivity and a conductive silicon substrate is used, and passive elements and an active element are formed on the same substrate. Alternatively, a cavity is provided in the conductive substrate directly beneath the SOI layer in the region where the passive elements are formed, thereby attaining the object.Type: ApplicationFiled: March 26, 2003Publication date: October 7, 2004Applicant: Hitachi, Ltd.Inventors: Masao Kondo, Katsuyoshi Washio, Masatada Horiuchi
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Patent number: 6785477Abstract: A large time constant is caused due to parasitic capacitance at an anode terminal of a photodetector of an optical receiver. Therefore, an optical receiver wherein a variable negative capacitor mainly including an NPN-type transistor operable at high speed is configured and is connected to the input terminal of a preamplifier to which the output of the photodetector is input so that parasitic capacitance caused in the photodetector and due to packaging is equivalently reduced and the fluctuation of parasitic capacitance caused due to manufacturing dispersion is also compensated is provided.Type: GrantFiled: September 19, 2000Date of Patent: August 31, 2004Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Toru Masuda, Katsuyoshi Washio, Taizo Yoshikawa, Eiji Ohue, Kenichi Ohhata
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Publication number: 20040129982Abstract: A semiconductor device having an MODFET and at least one other device formed on one identical semiconductor substrate, in which an intrinsic region for the MODFET is formed by selective growth in a groove formed on a semiconductor substrate having an insulation film on the side wall of the groove, and single-crystal silicon at the bottom of the groove, is disclosed. The step between the MODFET and the at least one other device mounted together on one identical substrate can be thereby decreased, and each of the devices can be reduced in the size and integrated to a high degree, and the interconnection length can be shortened to reduce power consumption.Type: ApplicationFiled: December 18, 2003Publication date: July 8, 2004Applicant: Renesas Technology CorporationInventors: Katsuya Oda, Katsuyoshi Washio
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Publication number: 20040113699Abstract: There is provided not only a radio frequency power amplifier using an SiGe HBT subject to a little amplification distortion, but also a communication system using the same. A conventional radio frequency power amplifier provides base bias paths of transistors Q1 through QN (SiGe HBT) with bias resistors R11 through R1N having resistance values three to five times higher than those of a ballast resistor attached to each transistor's base. A coil LB is provided in parallel with the bias resistor as a means for compensating a voltage drop due to direct current component IDC flowing through the bias resistor. Addition of the bias resistor suppresses non-linearity of low-frequency variations in an output current. Addition of the coil compensates for voltage drop. Accordingly, the maximum linear output power can be improved. As a result, it is possible to provide the power amplifier subject to a little amplification distortion within a wide output range.Type: ApplicationFiled: October 21, 2003Publication date: June 17, 2004Applicant: Renesas Technology Corp.Inventors: Masao Kondo, Toru Masuda, Katsuyoshi Washio
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Publication number: 20040108559Abstract: With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.Type: ApplicationFiled: September 30, 2003Publication date: June 10, 2004Applicant: Renesas Technology Corp.Inventors: Nobuyuki Sugii, Kazuhiro Ohnishi, Katsuyoshi Washio
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Patent number: 6723541Abstract: A method of producing a strain-relaxed Si—Ge virtual substrate for use in a semiconductor substrate which is planar and of less defects for improving the performance of a field effect semiconductor device, which method comprises covering an Si—Ge layer formed on an SOI substrate with an insulating layer to prevent evaporation of Ge, heating the mixed layer of silicon and germanium at a temperature higher than a solidus curve temperature determined by the germanium content of the Si—Ge layer into a partially melting state, and diffusing germanium to the Si layer on the insulating layer, thereby solidifying the molten Si—Ge layer to obtain a strain-relaxed Si—Ge virtual substrate.Type: GrantFiled: June 7, 2002Date of Patent: April 20, 2004Assignee: Hitachi, Ltd.Inventors: Nobuyuki Sugii, Shinya Yamaguchi, Katsuyoshi Washio
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Patent number: 6724019Abstract: A semiconductor device having an MODFET and at least one other device formed on one identical semiconductor substrate, in which an intrinsic region for the MODFET is formed by selective growth in a groove formed on a semiconductor substrate having an insulation film on the side wall of the groove, and single-crystal silicon at the bottom of the groove, is disclosed. The step between the MODFET and the at least one other device mounted together on one identical substrate can be thereby decreased, and each of the devices can be reduced in the size and integrated to a high degree, and the interconnection length can be shortened to reduce power consumption.Type: GrantFiled: April 3, 2001Date of Patent: April 20, 2004Assignee: Renesas Technology CorporationInventors: Katsuya Oda, Katsuyoshi Washio
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Patent number: 6667489Abstract: A high-speed heterojunction bipolar transistor in a large injection of electrons from the emitter and a method for production thereof. In a typical example of the SiGeC heterojunction bipolar transistor, the collector has a layer of n-type single-crystal Si and a layer of n-type single-crystal SiGe, the base is a layer of heavily doped p-type single-crystal SiGeC, and the emitter is a layer of n-type single-crystal Si. At the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC, the bandgap of the p-type single-crystal SiGeC is larger than that of the layer of n-type single-crystal SiGe. Even though the effective neutral base expands due to an increase in electrons injected from the emitter, no energy barrier occurs in the conduction band at the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC.Type: GrantFiled: November 20, 2002Date of Patent: December 23, 2003Assignee: Hitachi, Ltd.Inventors: Isao Suzumura, Katsuya Oda, Katsuyoshi Washio
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Patent number: 6658217Abstract: An optical receiver generates a voltage signal having a predetermined swing from a current signal, and feeds the voltage signal to a decision circuit. An optical receiving element receives the input optical signal, converts the optical signal to a current signal, and provides the current signal to a preamplifier, which converts the input current signal into a voltage signal. The voltage signal is input to an amplifier having a limiting function, which linearly amplifies the voltage signal when the swing of the voltage signal is smaller than a predetermined value, and limitedly amplifies the voltage signal when the voltage signal is greater than the predetermined value. An automatic-gain-control amplifier receives the output from the amplifier with the limiting function, and amplifies the input voltage signal to a voltage signal having a constant swing.Type: GrantFiled: September 6, 2001Date of Patent: December 2, 2003Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kenichi Ohhata, Ryoji Takeyari, Toru Masuda, Katsuyoshi Washio, Yasushi Hatta
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Patent number: 6653715Abstract: A bipolar transistor using a B-doped Si and Ge alloy for a base in which a Ge content in an emitter-base depletion region and in a base-collector depletion region is greater than a Ge content in a base layer. Diffusion of B from the base layer can be suppressed by making the Ge content in the emitter-base depletion region and in a base-collector depletion region on both sides of the base layer greater than the Ge content in the base layer since the diffusion coefficient of B in the SiGe layer is lowered as the Ge contents increases.Type: GrantFiled: September 10, 2002Date of Patent: November 25, 2003Assignee: Hitachi, Ltd.Inventors: Masao Kondo, Katsuya Oda, Katsuyoshi Washio
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Publication number: 20030205722Abstract: A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.Type: ApplicationFiled: June 10, 2003Publication date: November 6, 2003Inventors: Katsuyoshi Washio, Reiko Hayami, Hiromi Shimamoto, Masao Kondo, Katsuya Oda, Eiji Oue, Masamichi Tanabe