Patents by Inventor Katsuyuki Seki
Katsuyuki Seki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8669183Abstract: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.Type: GrantFiled: May 18, 2007Date of Patent: March 11, 2014Assignees: SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Akira Suzuki, Katsuyuki Seki, Koujiro Kameyama, Takahiro Oikawa
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Patent number: 8426949Abstract: A mesa type semiconductor device and its manufacturing method are offered to increase a withstand voltage as well as reducing a leakage current. An N?-type semiconductor layer is formed on a surface of a semiconductor substrate, and a P-type semiconductor layer is formed on the N?-type semiconductor layer. After that, a mesa groove is formed by etching the P-type semiconductor layer, a PN junction, the N?-type semiconductor layer and a partial thickness of the semiconductor substrate so that a width of the mesa groove grows from a surface of the P-type semiconductor layer toward the semiconductor substrate. Subsequent wet etching removes a damaged layer in an inner wall of the mesa groove caused by the preceding etching and transforms the mesa groove in a region close to a surface of the P-type semiconductor layer so that a width of the mesa groove increases toward the surface of the P-type semiconductor layer. After that, the semiconductor substrate and the layers stacked on it are diced.Type: GrantFiled: January 15, 2009Date of Patent: April 23, 2013Assignees: SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Katsuyuki Seki, Akira Suzuki, Keita Odajima
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Patent number: 8368181Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which enhance the yield and productivity. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the P type semiconductor layer on the outside of the mesa groove. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.Type: GrantFiled: December 18, 2008Date of Patent: February 5, 2013Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Akira Suzuki, Katsuyuki Seki, Keita Odajima
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Patent number: 8362595Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which minimize the manufacturing cost and prevents contamination and physical damage of the device. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the end portion of the anode electrode. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.Type: GrantFiled: December 18, 2008Date of Patent: January 29, 2013Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Akira Suzuki, Katsuyuki Seki, Keita Odajima
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Patent number: 8319317Abstract: Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N? type semiconductor layer and the thermal oxide film.Type: GrantFiled: June 9, 2009Date of Patent: November 27, 2012Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Katsuyuki Seki, Naofumi Tsuchiya, Akira Suzuki, Kikuo Okada
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Patent number: 8227901Abstract: This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment.Type: GrantFiled: June 11, 2009Date of Patent: July 24, 2012Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Katsuyuki Seki, Akira Suzuki, Keita Odajima, Kikuo Okada, Koujiro Kameyama
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Patent number: 8173543Abstract: The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus.Type: GrantFiled: July 26, 2007Date of Patent: May 8, 2012Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Katsuyuki Seki, Akira Suzuki, Koujiro Kameyama, Takahiro Oikawa
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Publication number: 20090309193Abstract: Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N? type semiconductor layer and the thermal oxide film.Type: ApplicationFiled: June 9, 2009Publication date: December 17, 2009Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.Inventors: Katsuyuki SEKI, Naofumi TSUCHIYA, Akira SUZUKI, Kikuo OKADA
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Publication number: 20090309194Abstract: This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment.Type: ApplicationFiled: June 11, 2009Publication date: December 17, 2009Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.Inventors: Katsuyuki SEKI, Akira Suzuki, Keita Odajima, Kikuo Okada, Koujiro Kameyama
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Publication number: 20090189257Abstract: A mesa type semiconductor device and its manufacturing method are offered to increase a withstand voltage as well as reducing a leakage current. An N?-type semiconductor layer is formed on a surface of a semiconductor substrate, and a P-type semiconductor layer is formed on the N?-type semiconductor layer. After that, a mesa groove is formed by etching the P-type semiconductor layer, a PN junction, the N?-type semiconductor layer and a partial thickness of the semiconductor substrate so that a width of the mesa groove grows from a surface of the P-type semiconductor layer toward the semiconductor substrate. Subsequent wet etching removes a damaged layer in an inner wall of the mesa groove caused by the preceding etching and transforms the mesa groove in a region close to a surface of the P-type semiconductor layer so that a width of the mesa groove increases toward the surface of the P-type semiconductor layer. After that, the semiconductor substrate and the layers stacked on it are diced.Type: ApplicationFiled: January 15, 2009Publication date: July 30, 2009Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.Inventors: Katsuyuki SEKI, Akira Suzuki, Keita Odajima
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Publication number: 20090160034Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which minimize the manufacturing cost and prevents contamination and physical damage of the device. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the end portion of the anode electrode. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.Type: ApplicationFiled: December 18, 2008Publication date: June 25, 2009Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.Inventors: Akira Suzuki, Katsuyuki Seki, Keita Odajima
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Publication number: 20090160035Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which enhance the yield and productivity. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the P type semiconductor layer on the outside of the mesa groove. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.Type: ApplicationFiled: December 18, 2008Publication date: June 25, 2009Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.Inventors: Akira SUZUKI, Katsuyuki SEKI, Keita ODAJIMA
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Publication number: 20080023846Abstract: The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus.Type: ApplicationFiled: July 26, 2007Publication date: January 31, 2008Applicants: SANYO ELECTRIC CO., LTD., Sanyo Semiconductor Co., Ltd.Inventors: Katsuyuki Seki, Akira Suzuki, Koujiro Kameyama, Takahiro Oikawa
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Publication number: 20070281474Abstract: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.Type: ApplicationFiled: May 18, 2007Publication date: December 6, 2007Applicants: Sanyo Electric Co., Ltd.Inventors: Akira Suzuki, Katsuyuki Seki, Koujiro Kameyama, Takahiro Oikawa