Patents by Inventor Kaushik Roy

Kaushik Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210142157
    Abstract: An electronic neuron device that includes a thresholding unit which utilizes current-induced spin-orbit torque (SOT). A two-step switching scheme is implemented with the device. In the first step, a charge current through heavy metal (HM) places the magnetization of a nano-magnet along the hard-axis (i.e. an unstable point for the magnet). In the second step, the device receives a current (from an electronic synapse) which moves the magnetization from the unstable point to one of the two stable states. The polarity of the net synaptic current determines the final orientation of the magnetization. A resistive crossbar array may also be provided which functions as the synapse generating a bipolar current that is a weighted sum of the inputs of the device.
    Type: Application
    Filed: August 20, 2020
    Publication date: May 13, 2021
    Applicant: Purdue Research Foundation
    Inventors: Abhronil Sengupta, Sri Harsha Choday, Yusung Kim, Kaushik Roy
  • Publication number: 20210117156
    Abstract: An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.
    Type: Application
    Filed: October 15, 2020
    Publication date: April 22, 2021
    Applicant: Purdue Research Foundation
    Inventors: Mustafa Ali, Akhilesh Jaiswal, Kaushik Roy
  • Patent number: 10825510
    Abstract: A method of obtaining an in-memory vector-based dot product is disclosed, which includes providing a matrix of memory cells having M rows, each memory cell in each row holding a value and having dedicated read transistors T1 and T2, where T1 is controlled by the value held in the associated memory cell and T2 is controlled by a row-dedicated source (vin) for each row, the combination of the T1 and T2 transistors for each cell selectively (i) couple a reference voltage with a column-dedicated read bit line (RBL) for each column for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column for a memory read operation, where total resistance of the read transistors (R) for each cell in each row is based on Rmax/2(M-1), . . . Rmax, where Rmax is the resistance of the least significant cell in each row.
    Type: Grant
    Filed: February 9, 2019
    Date of Patent: November 3, 2020
    Assignee: Purdue Research Foundation
    Inventors: Akhilesh Ramlaut Jaiswal, Amogh Agrawal, Kaushik Roy, Indranil Chakraborty
  • Patent number: 10802827
    Abstract: An in-situ in-memory implication gate is disclosed. The gate include a memory cell. The cell includes a first voltage source, a second voltage source lower in value than the first voltage source, a first and second magnetic tunneling junction devices (MTJ) selectively juxtaposed in a series and mirror imaged relationship between the first and second sources, each having a pinned layer (PL) in a first direction and a free layer (FL) having a polarity that can be switched from the first direction in which case the MTJ is in a parallel configuration presenting an electrical resistance to current flow below a first resistance threshold to a second direction in which case the MTJ is in an anti-parallel configuration presenting an electrical resistance to current flow higher than a second resistance threshold, and further each having a non-magnetic layer (NML) separating the PL from the FL.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: October 13, 2020
    Assignee: Purdue Research Foundation
    Inventors: Akhilesh Ramlaut Jaiswal, Amogh Agrawal, Kaushik Roy
  • Publication number: 20200258569
    Abstract: A method of obtaining an in-memory vector-based dot product is disclosed, which includes providing a matrix of memory cells having M rows, each memory cell in each row holding a value and having dedicated read transistors T1 and T2, where T1 is controlled by the value held in the associated memory cell and T2 is controlled by a row-dedicated source (vin) for each row, the combination of the T1 and T2 transistors for each cell selectively (i) couple a reference voltage with a column-dedicated read bit line (RBL) for each column for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column for a memory read operation, where total resistance of the read transistors (R) for each cell in each row is based on Rmax/2(M-1), . . . Rmax, where Rmax is the resistance of the least significant cell in each row.
    Type: Application
    Filed: February 9, 2019
    Publication date: August 13, 2020
    Applicant: Purdue Research Foundation
    Inventors: Akhilesh Ramlaut Jaiswal, Amogh Agrawal, Kaushik Roy, Indranil Chakraborty
  • Patent number: 10734052
    Abstract: A bit cell driving mechanism is disclosed. The mechanism includes a bit cell which includes a first magnetic tunnel junction (MTJ) cell, including a pinned layer, a non-magnetic layer, a free layer having two magnetic regions separated by a laterally moveable domain wall, and a spin-hall metal layer configured to receive an electrical current therethrough which causes the DW to move laterally. The mechanism also includes a second MTJ cell coupled to the first MTJ cell as well as an interconnect driver configured to provide electrical current to the first MTJ cell during a write operation.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 4, 2020
    Assignee: Purdue Research Foundation
    Inventors: Zubair Al Azim, Ankit Sharma, Kaushik Roy
  • Publication number: 20200182951
    Abstract: A current sensing system, comprising at least one magnetic tunnel junction device placed adjacent to a current carrying conductor electrically connected to a battery of a vehicle. The magnetic tunnel junction device is configured to measure a magnetic field around the conductor. A monitoring device is operatively connected to the magnetic tunnel junction device, wherein the monitoring device is configured to receive the magnetic field measurement and determine an estimate of the current flowing through the conductor.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 11, 2020
    Inventors: Kaushik Roy, Byunghoo Jung
  • Patent number: 10592802
    Abstract: An electronic synapse is disclosed, comprising a heavy metal layer having a high spin orbit coupling, a domain wall magnet layer having a bottom surface adjacent to a top surface of the heavy metal layer, the domain wall magnet layer having a perpendicular magnetic anisotropy, the domain wall magnet layer having a domain wall, the domain wall running parallel to a longitudinal axis of the domain wall magnet layer, a pinned layer having perpendicular magnetic anisotropy, and an oxide tunnel barrier connected between the domain wall magnet layer and the pinned layer, wherein the pinned layer, the oxide tunnel barrier, and the free layer form a magnetic tunnel junction.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 17, 2020
    Assignee: Purdue Research Foundation
    Inventors: Abhronil Sengupta, Zubair Al Azim, Xuanyao Kelvin Fong, Kaushik Roy
  • Publication number: 20200051155
    Abstract: Methods, systems, and computer readable media for detecting customer presence to initiate the ordering and purchase of goods and services are disclosed. In one example, a system includes a detection server configured to detect the presence of a mobile device in a designated area associated with a merchant location and for initiating a menu selection application in the mobile device for placing an order for at least one product. The system further includes a merchant server configured to receive, from the mobile device, purchase order data associated with the order for the at least one product, a customer identifier associated with the mobile device, and a location identifier associated with the designated area, and for utilizing the customer identifier to send a notification message that indicates that the at least one product is available to the mobile device.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Mohammad Khan, Kaushik Roy
  • Patent number: 10496832
    Abstract: Systems and methods for providing trust provisioning are disclosed. A utilization request requesting to utilize data stored by a secure element associated with the device may be processed by a software application. In response to processing the utilization request, a registration request message for registering the software application may be communicated to a management server. A validation code may be received from the management server in reply to the registration request message. The received validation code may be verified to match a second validation code. Subsequent to successful verification, a passcode and an identifier of the secure element may be communicated to the management server. In response to communicating the passcode and the secure element identifier, an acknowledgement may be received from the management server specifying whether registration of the software application was successful.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 3, 2019
    Assignee: GFA Worldwide, Inc.
    Inventors: David Brudnicki, Kaushik Roy, Patrick Lim
  • Patent number: 10489846
    Abstract: Methods, systems, and computer readable media for detecting customer presence to initiate the ordering and purchase of goods and services are disclosed. In one example, a system includes a detection server configured to detect the presence of a mobile device in a designated area associated with a merchant location and for initiating a menu selection application in the mobile device for placing an order for at least one product. The system further includes a merchant server configured to receive, from the mobile device, purchase order data associated with the order for the at least one product, a customer identifier associated with the mobile device, and a location identifier associated with the designated area, and for utilizing the customer identifier to send a notification message that indicates that the at least one product is available to the mobile device.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: November 26, 2019
    Assignee: MASTERCARD INTERNATIONAL INCORPORATED
    Inventors: Mohammad Khan, Kaushik Roy
  • Patent number: 10476487
    Abstract: An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: November 12, 2019
    Assignee: Purdue Research Foundation
    Inventors: Kaushik Roy, Mrigank Sharad
  • Publication number: 20190258482
    Abstract: An in-situ in-memory implication gate is disclosed. The gate include a memory cell. The cell includes a first voltage source, a second voltage source lower in value than the first voltage source, a first and second magnetic tunneling junction devices (MTJ) selectively juxtaposed in a series and mirror imaged relationship between the first and second sources, each having a pinned layer (PL) in a first direction and a free layer (FL) having a polarity that can be switched from the first direction in which case the MTJ is in a parallel configuration presenting an electrical resistance to current flow below a first resistance threshold to a second direction in which case the MTJ is in an anti-parallel configuration presenting an electrical resistance to current flow higher than a second resistance threshold, and further each having a non-magnetic layer (NML) separating the PL from the FL.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 22, 2019
    Applicant: Purdue Research Foundation
    Inventors: Akhilesh Ramlaut Jaiswal, Amogh Agrawal, Kaushik Roy
  • Publication number: 20190220412
    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.
    Type: Application
    Filed: March 24, 2019
    Publication date: July 18, 2019
    Applicant: Purdue Research Foundation
    Inventors: Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan
  • Publication number: 20190197101
    Abstract: A computing system is described that includes user interface components configured to receive typed user input; and one or more processors. The one or more processors are configured to: receive, by a computing system and at a first time, a first portion of text typed by a user in an electronic message being edited; predict, based on the first portion of text, a first candidate portion of text to follow the first portion of text; output, for display, the predicted first candidate portion of text for optional selection to append to the first portion of text; determine, at a second time that is after the first time, that the electronic message is directed to a sensitive topic; and responsive to determining that the electronic message is directed to a sensitive topic, refrain from outputting subsequent candidate portions of text for optional selection to append to text in the electronic message.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Inventors: Paul Roland Lambert, Timothy Youngjin Sohn, Jacqueline Amy Tsay, Gagan Bansal, Cole Austin Bevis, Kaushik Roy, Justin Tzi-jay LU, Katherine Anna Evans, Tobias Bosch, Yinan Wang, Matthew Vincent Dierker, Gregory Russell Bullock, Ettore Randazzo, Tobias Kaufmann, Yonghui Wu, Benjamin N. Lee, Xu Chen, Brian Strope, Yun-hsuan Sung, Do Kook Choe, Rami Eid Sammour Al-Rfou'
  • Publication number: 20190122716
    Abstract: A bit cell driving mechanism is disclosed. The mechanism includes a bit cell which includes a first magnetic tunnel junction (MTJ) cell, including a pinned layer, a non-magnetic layer, a free layer having two magnetic regions separated by a laterally moveable domain wall, and a spin-hall metal layer configured to receive an electrical current therethrough which causes the DW to move laterally. The mechanism also includes a second MTJ cell coupled to the first MTJ cell as well as an interconnect driver configured to provide electrical current to the first MTJ cell during a write operation.
    Type: Application
    Filed: October 23, 2018
    Publication date: April 25, 2019
    Applicant: Purdue Research Foundation
    Inventors: Zubair Al Azim, Ankit Sharma, Kaushik Roy
  • Patent number: 10255186
    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: April 9, 2019
    Assignee: Purdue Research Foundation
    Inventors: Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan
  • Publication number: 20180365154
    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.
    Type: Application
    Filed: June 14, 2017
    Publication date: December 20, 2018
    Applicant: Purdue Research Foundation
    Inventors: Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan
  • Patent number: 10073733
    Abstract: A memory capable of carrying out compute-in-memory (CiM) operations is disclosed. The memory includes a matrix of bit cells having a plurality of bit cells along one or more rows and a plurality of bit cells along one or more columns, each bit cell having a value stored therein, an address decoder configured to receive addresses and activate two or more of the rows associated with the addresses, and a sensing circuit coupled to each column of bit cells, and configured to provide two or more outputs, wherein each output is associated with at least one compute operation performed on values stored in the bit cells in the column.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 11, 2018
    Assignee: Purdue Research Foundation
    Inventors: Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan
  • Publication number: 20180114216
    Abstract: A method, electronic device, and non-transitory computer readable medium for a mobile wallet remittance are provided. The method includes receiving a request to remit money from a sender to a receiver, wherein the request includes transaction information. The method also includes generating a list of eligible providers from a plurality of providers based on the transaction information. Additionally, the method includes notifying a provider to transfer the money when an indication is received that a provider is selected from the list of eligible providers.
    Type: Application
    Filed: October 20, 2017
    Publication date: April 26, 2018
    Inventors: Vinod Cherian Joseph, Tuomo Sipila, Homayoon Shahinfar, Kaushik Roy