Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The synchronous data stage is between a first wave pipeline data stage of the plurality of wave pipeline data stages and a second wave pipeline data stage of the plurality of wave pipeline data stages. The clock path corresponds to the plurality of wave pipeline data stages. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

Abstract: A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.

Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The synchronous data stage is between a first wave pipeline data stage of the plurality of wave pipeline data stages and a second wave pipeline data stage of the plurality of wave pipeline data stages. The clock path corresponds to the plurality of wave pipeline data stages. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage between a data input node and a data output node. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The clock path includes a plurality of clock stages corresponding to the plurality of wave pipeline data stages between an input clock node and a return clock node. Each clock stage has a delay configured to be equal to a delay of the corresponding wave pipeline data stage. The wave pipeline includes a second data latch to latch the data on the data output node in response to a return clock signal on the return clock node. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

Abstract: A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage between a data input node and a data output node. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The clock path includes a plurality of clock stages corresponding to the plurality of wave pipeline data stages between an input clock node and a return clock node. Each clock stage has a delay configured to be equal to a delay of the corresponding wave pipeline data stage. The wave pipeline includes a second data latch to latch the data on the data output node in response to a return clock signal on the return clock node. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.

Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

Abstract: A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.

Abstract: A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.

Abstract: A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.

Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

Abstract: Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.

Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.