Abstract: A method to protect code against altering includes reading immutable boot code from a ROM. A code image is loaded from an external memory and a hash is calculated by a core unit. The hash is initially authenticated using the boot code for decrypting the hash of the external memory. A salted hash for each equivalent of a cache line of the code image is concurrently calculated by a cache protection block and the salted hash for each cache line in an internal hash table is stored. If the authentication succeeds, a part of the code image is loaded into a secure cache of the embedded micro-processor.

Abstract: The disclosure discloses a method, the method includes: reading immutable boot code from a ROM; loading a code image from an external memory and calculating a hash by a core unit; initially authenticating the hash using the boot code for decrypting the hash of the external memory; whereas concurrently calculating a salted hash for each equivalent of a cache line of the code image by a cache protection block; storing the salted hash for each cache line in an internal hash table; whereas if the authentication succeeds, a part of the code image is loaded into a secure cache of the embedded micro-processor; otherwise if a secure cache miss occurs, the code image is reloaded from the external memory and the salted hash for the missed cache line is re-calculated by the cache protecting block and is checked against the stored salted hash in the internal hash table.

Abstract: A circuit for software tracing in a system on chip is described as including a plurality of components, each component having at least one local processor connected to a first communication bus; and each component being connected to a second communication bus. The circuit may further include a separate trace data bus being configured to transmit trace data generated by code running on the components. A method associated with software tracing on such a circuit is also disclosed.

Abstract: Implementations relate to a hybrid finite state machine that is based on a micro-coded processor and the use of look-up tables to implement combinational logic. Micro-coding is used to describe the state transitions of the FSM and look-up tables are used to determine the conditions for state transitions and to generate the outputs as a function of the state.

Abstract: An apparatus and method are described for performing a low overhead error checking and correction. For example, one embodiment of an electronic circuit comprises: one or more memories to store data or instructions in rows and columns, and to further store row parity data comprising a parity value associated with each row and column parity data comprising a parity value associated with each column; and error checking logic to perform a row parity check to detect if errors exist in any of the rows, wherein if an error is detected in one of the rows, the error checking and correction logic is to perform a column parity check to identify a column in which the detected error occurred; and error correction logic to correct the detected error using the detected row and column identified by the error checking logic.

Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

Abstract: A DMA controller with general programmability and functionality is described. The DMA controller includes a bus interface coupled to an internal memory domain and an external memory domain and general purpose input and output lines. The DMA controller also includes a set of instruction registers that can store (and a processing unit to execute) instructions to transfer data using the bus interface and to read or write signals on the general purpose lines.

Abstract: A clock domain separation device and a method for operating the device is provided for separating two clock domains of a bus system in a system-on-chip (SoC). The clock domain separation device is a hardware module that acts as a guarding between the two clock domains that contain either bus end, and is generally applicable with handshake-type bus protocols. The clock domain separation module allows for each clock domain to switch its clock on and off independently from the state of the other clock domains, without risking data loss or protocol violation.

Abstract: A circuit arrangement includes a plurality of functional units each of which comprises a plurality of data processing modules and a local controller. The plurality of data processing modules run a common system clock and are connected by a streaming data bus running a handshake-type streaming data transfer protocol. A profiling module of the circuit arrangement assesses control signals tapped at predefined interfaces of the streaming data bus during real time operation, for determining link performance and communication patterns for profiling and debugging purposes, and hence constitutes a simple and low cost approach for assessing intra-component and inter-component link performance and communication patterns on large SoCs. A method for profiling data flow for use in such a circuit arrangement is also provided.

Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.

Abstract: A circuit for software tracing in a system on chip is described as including a plurality of components, each component having at least one local processor connected to a first communication bus; and each component being connected to a second communication bus. The circuit may further include a separate trace data bus being configured to transmit trace data generated by code running on the components. A method associated with software tracing on such a circuit is also disclosed.

Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

Abstract: Implementations relate to a hybrid finite state machine that is based on a micro-coded processor and the use of look-up tables to implement combinational logic. Micro-coding is used to describe the state transitions of the FSM and look-up tables are used to determine the conditions for state transitions and to generate the outputs as a function of the state.

Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

Abstract: Failure and repair information collected during self-testing of arrays in an integrated circuit is stored in a centralized array in the integrated circuit. In that way, a centralized array can be read out to provide failure and repair information on the arrays in the integrated circuit rather than having to read from each array. In addition, the failure and repair information may also be stored in the array under test for certain of the arrays.

Abstract: In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.

Abstract: A USB (Universal Serial Bus) controller technique for implementing OTG (On-The-Go) functionality is provided. The device may have an EHCI (Enhanced Host Controller Interface) compliant host control unit, and an OTG control unit to implement an OTG state machine partly in hardware and partly in software. The OTG control unit may have an OTG control register and an OTG status register which are accessible by software. Further, the USB controller device may have a device control unit to implement device functionality and a port multiplexer to assign a physical port to either the host or the device control unit. The OTG control unit may be comprised in the port multiplexer. Further, a software driver may read the OTG status register in response to receiving an interrupt from the USB controller device, and write to the OTG control register to force the USB controller device to change its OTG state.

Abstract: A circuit arrangement includes a plurality of functional units each of which comprises a plurality of data processing modules and a local controller. The plurality of data processing modules run a common system clock and are connected by a streaming data bus running a handshake-type streaming data transfer protocol. A profiling module of the circuit arrangement assesses control signals tapped at predefined interfaces of the streaming data bus during real time operation, for determining link performance and communication patterns for profiling and debugging purposes, and hence constitutes a simple and low cost approach for assessing intra-component and inter-component link performance and communication patterns on large SoCs. A method for profiling data flow for use in such a circuit arrangement is also provided.

Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, MBST circuitry is used set memory elements of arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage. Preferably, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays.

Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.