Abstract: A USB (Universal Serial Bus) host controller, a corresponding integrated circuit chip, a computer system and an operation method are provided for handling the data traffic between at least one USB device and the computer system having system memory. A transaction processing unit processes transactions to or from the at least one USB device. Further, a transaction duration management unit is provided for determining estimated duration values of the transactions. The transaction processing unit is adapted to process the transactions dependent on the estimated duration values. A descriptor-to-transaction converter may be provided, and the prefetched mechanism may be made dependent on a threshold value relating to the estimated duration values.

Abstract: A data storage mechanism is provided where a plurality of data items are stored in a plurality of register elements. Each registered element is capable of storing at least one data item. The plurality of register elements is arranged to form a sequence of register elements. First data is stored in a first part of the sequence and second data is stored in a second part of the sequence. The first part and the second part are of variable lengths with the sum of the variable lengths being equal to the lengths of the sequence of register elements. Thus, a double-ended queue mechanism is provided which may be used to store data of different type or data which is either scheduled periodically or asynchronously. The mechanism may be used in a USB 2.0 compliant host controller.

Abstract: A USB host controller is provided for handling the data traffic between at least one USB device and a system memory of a computer system. The USB host controller comprises a data fetch unit for fetching data elements from the system memory, a storage unit for storing the fetched data elements, and a transaction processing unit for processing transactions sent to or received from the USB device dependent on the fetched data elements stored in the storage unit. The data fetch unit and the transaction processing unit are arranged for operating asynchronously. The host controller may be USB 2.0 compliant and may be realized in a southbridge.

Abstract: A DMA (Direct Memory Access) mechanism is provided that may be of improved performance in particular in connection with high-speed packet buses. A transmit DMA engine for outputting read requests for a memory interface and receiving requested data from the memory interface, comprises a data transfer initiating unit for outputting first address data identifying a first memory range. Further, a boundary alignment unit is provided for generating second address data using the first address data, where the second address data identifies a second memory range that differs from the first memory range in at least one boundary. Further a corresponding boundary alignment may be done in a receive DMA engine. The DMA mechanism may be performed in a USB-2 host controller that has HyperTransport capabilities.