Patents by Inventor Kazuaki Ano
Kazuaki Ano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8310069Abstract: The symbolization of a semiconductor device (100) is incorporated in a thin sheet (130) attached to the top of the device, facing outwardly with its bare surface. The material of the sheet (about 1 to 10 ?m thick) includes regions of a first optical reflectivity and a first color, and regions (133) of a second optical reflectivity and a second color, which differ from, and contrast with, the first reflectivity and color. Preferred choices for the sheet material include the compound o-cresol novolac epoxy and the compound bisphenol-A, more preferably with the chemical imidazole added to the film material. A preferred embodiment of the invention is a packaged device with a semiconductor chip a (101) connected to a substrate (102); the connection is achieved by bonding wires (111) forming an arch with a top 111a. The chip, the wire arches, and the substrate are embedded in an encapsulation material (120), which borders on the attached top sheet so that the arch tops touch the border (131).Type: GrantFiled: September 16, 2008Date of Patent: November 13, 2012Assignee: Texas Instruements IncorporatedInventors: Kazuaki Ano, Wen Yu Lee
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Patent number: 8058706Abstract: A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ?5% less than a cross sectional area of the top surface to provide a protruding lip having a bottom lip surface. A package substrate includes a top substrate surface including substrate bonding sites, a bottom substrate surface, and a die support structure on the top substrate surface having a gap region. The bottom lip surface of the IC die is secured to the die support structure and the bottom surface of the IC die extends below the die support structure into the gap region. Coupling connectors couple the bonding features on the IC die to the substrate bonding sites.Type: GrantFiled: September 8, 2009Date of Patent: November 15, 2011Assignee: Texas Instruments IncorporatedInventors: Chien-Te Feng, Kazuaki Ano, Frank Yu, Trevor Liu
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Publication number: 20110136335Abstract: A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic compound. A solder element (308) including tin is metallurgically attached to the alloy layer across the pad area. No fraction of the original thin nickel layer is left after the reflow process. Copper/tin alloys help to improve the drop test performance, nickel/copper/tin alloys help to improve the life test performance.Type: ApplicationFiled: January 18, 2011Publication date: June 9, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Kazuaki Ano
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Publication number: 20110057296Abstract: A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ?5% less than a cross sectional area of the top surface to provide a protruding lip having a bottom lip surface. A package substrate includes a top substrate surface including substrate bonding sites, a bottom substrate surface, and a die support structure on the top substrate surface having a gap region. The bottom lip surface of the IC die is secured to the die support structure and the bottom surface of the IC die extends below the die support structure into the gap region. Coupling connectors couple the bonding features on the IC die to the substrate bonding sites.Type: ApplicationFiled: September 8, 2009Publication date: March 10, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: CHIEN-TE FENG, KAZUAKI ANO, FRANK YU, TREVOR LIU
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Patent number: 7893544Abstract: A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic compound. A solder element (308) including tin is metallurgically attached to the alloy layer across the pad area. No fraction of the original thin nickel layer is left after the reflow process. Copper/tin alloys help to improve the drop test performance, nickel/copper/tin alloys help to improve the life test performance.Type: GrantFiled: May 8, 2007Date of Patent: February 22, 2011Assignee: Texas Instruments IncorporatedInventor: Kazuaki Ano
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Publication number: 20110001227Abstract: A semiconductor device (100) with two leads (103) of a leadframe (101) extending from opposite directions towards each other, the leads having tips (103b) curled as springs acting to exert pressure force in the direction of the leads, the two curls spaced apart by a distance operable to secure a semiconductor chip; device (100) further has a semiconductor chip (110) with width (115) and sidewalls (112) clamped in the distance between the two curls, the chip secured to the leadframe by the friction based on the pressure force of the curls.Type: ApplicationFiled: June 2, 2010Publication date: January 6, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Kazuaki Ano
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Patent number: 7829389Abstract: A low-viscosity resin is deposited using an apparatus with a movable and heatable wheel and a heater stage. A tape is provided, which includes a layer (140) of an adhesive polymeric resin and a film (141) of an inert plastic compound. The tape is wrapped around the wheel (150) so that the film touches the wheel and the layer faces away from the wheel. The wheel is heated to a temperature high enough to transits the polymeric resin into a low-viscosity state. A substrate strip (110), which has been assembled with a plurality of semiconductor chips (101) connected to the substrate by bonding wires (120), is placed on a station (130) also heated to the transition temperature. The wheel is then moved to roll the low viscosity resin on the chips and wires along the strip, while the inert film is separated. The chips and wires are thus encapsulated.Type: GrantFiled: October 1, 2008Date of Patent: November 9, 2010Assignee: Texas Instruments IncorporatedInventor: Kazuaki Ano
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Publication number: 20090236715Abstract: The invention relates to microelectronic semiconductor chip assemblies having vertically stacked layers. In a disclosed example of a preferred embodiment, a vertically stacked semiconductor chip assembly includes a first semiconductor chip affixed to the surface of a substrate. A laminated interposing layer therebetween includes a first adhesive material and a second adhesive material, at least one of the adhesive materials adapted to capturing debris. Methods are disclosed for making a vertically stacked semiconductor chip assemblies by joining first and second adhesive materials to form a laminated interposing layer between a first chip and second chip or substrate. In preferred embodiments of the invention, the interposing layer includes polyimide film and one adhesive material of relatively low elasticity, and another adhesive material having relatively high elasticity.Type: ApplicationFiled: March 18, 2008Publication date: September 24, 2009Inventors: Kazuaki Ano, Frank Yu, Wei Lung Hsu
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Publication number: 20090108433Abstract: Methods for assembling multilayer semiconductor device packages are disclosed. A base substrate having device mounting sites is provided. A number of semiconductor devices are connected to the device mounting sites. Upper boards are attached to the base substrate and over each of the coupled devices. The method includes steps of testing one or more of the base substrate, semiconductor device, or upper board, prior to operably connecting one to another.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Inventors: Kenji Masumoto, Kazuaki Ano
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Publication number: 20090091029Abstract: The symbolization of a semiconductor device (100) is incorporated in a thin sheet (130) attached to the top of the device, facing outwardly with its bare surface. The material of the sheet (about 1 to 10 ?m thick) includes regions of a first optical reflectivity and a first color, and regions (133) of a second optical reflectivity and a second color, which differ from, and contrast with, the first reflectivity and color. Preferred choices for the sheet material include the compound o-cresol novolac epoxy and the compound bisphenol-A, more preferably with the chemical imidazole added to the film material. A preferred embodiment of the invention is a packaged device with a semiconductor chip a (101) connected to a substrate (102); the connection is achieved by bonding wires (111) forming an arch with a top 111a. The chip, the wire arches, and the substrate are embedded in an encapsulation material (120), which borders on the attached top sheet so that the arch tops touch the border (131).Type: ApplicationFiled: September 16, 2008Publication date: April 9, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kazuaki Ano, Wen Yu Lee
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Publication number: 20090093088Abstract: A low-viscosity resin is deposited using an apparatus with a movable and heatable wheel and a heater stage. A tape is provided, which includes a layer (140) of an adhesive polymeric resin and a film (141) of an inert plastic compound. The tape is wrapped around the wheel (150) so that the film touches the wheel and the layer faces away from the wheel. The wheel is heated to a temperature high enough to transits the polymeric resin into a low-viscosity state. A substrate strip (110), which has been assembled with a plurality of semiconductor chips (101) connected to the substrate by bonding wires (120), is placed on a station (130) also heated to the transition temperature. The wheel is then moved to roll the low viscosity resin on the chips and wires along the strip, while the inert film is separated. The chips and wires are thus encapsulated.Type: ApplicationFiled: October 1, 2008Publication date: April 9, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Kazuaki Ano
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Publication number: 20080230880Abstract: The invention provides improved rivet and heat sink arrangements in leadframes and IC packages. The invention discloses a semiconductor device leadframe array with numerous leadframes having integrated circuit sites provided for receiving individual integrated circuit chips. Support strips are arranged adjacent to and supporting the integrated circuit sites in an array of one or more rows. Package areas provided each include one or integrated circuit site for ultimate encapsulation in an integrated circuit package. Rivet points are located on the support strips outside of the package areas. An array of heat sinks having corresponding rivet points is riveted to the leadframe array to complete the assembly. Alternative embodiments of the invention provide apparatus and methods for the assembly of an integrated circuit package with a leadframe having an operably coupled integrated circuit chip.Type: ApplicationFiled: January 14, 2008Publication date: September 25, 2008Inventors: Kazuaki Ano, Vincent Feng
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Publication number: 20080179761Abstract: The package (105) of a semiconductor chip has a surface (105a) of optical reflection and color, and is substantially free of indentations; the material of the package may be selected from a group consisting of polymers, molding compound, ceramics, metals, and semiconductors. The surface includes symbols, which contrast optically with the surface. The symbols include lines of approximately circular vapor-deposited spots (110) of ink particles. The spots have a diameter and a thickness of substantially bell-shaped distribution across the diameter; the spots may also overlap.Type: ApplicationFiled: January 14, 2008Publication date: July 31, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Kazuaki Ano
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Patent number: 7350293Abstract: A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder balls and the second openings configured to accommodate circuit chips. A copper foil is laminated on the adhesive layer, and the portion of this copper foil in the second openings is mechanically shaped into a position coplanar with the second surface, whereby it becomes useable as a chip mount pad, exposed after encapsulation for low resistance heat dissipation. The circuit chips are mounted by means of a thermally conductive material on each of the chip mount pads. Encapsulating material surrounds the mounted chips in low profile. For ball grid array devices, solder balls are attached to the copper foil exposed by the first openings in the tape.Type: GrantFiled: March 22, 2006Date of Patent: April 1, 2008Assignee: Texas Instruments IncorporatedInventor: Kazuaki Ano
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Publication number: 20070284740Abstract: A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic compound. A solder element (308) including tin is metallurgically attached to the alloy layer across the pad area. No fraction of the original thin nickel layer is left after the reflow process. Copper/tin alloys help to improve the drop test performance, nickel/copper/tin alloys help to improve the life test performance.Type: ApplicationFiled: May 8, 2007Publication date: December 13, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Kazuaki Ano
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Patent number: 7233074Abstract: A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic compound. A solder element (308) including tin is metallurgically attached to the alloy layer across the pad area. No fraction of the original thin nickel layer is left after the reflow process. Copper/tin alloys help to improve the drop test performance, nickel/copper/tin alloys help to improve the life test performance.Type: GrantFiled: August 11, 2005Date of Patent: June 19, 2007Assignee: Texas Instruments IncorporatedInventor: Kazuaki Ano
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Patent number: 7192861Abstract: An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded to said contact pad. This interconnect includes a wire (304) attached to the pad by ball bonding (305), a loop (306) in the wire closed by bonding the wire to itself (307) near the ball, and a portion (307) of the remainder of the wire extended approximately parallel to the surface. The interconnect can be confined to a space (308) equal to or less than three ball heights from the surface.Type: GrantFiled: September 28, 2004Date of Patent: March 20, 2007Assignee: Texas Instruments IncorporatedInventor: Kazuaki Ano
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Publication number: 20070035023Abstract: A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic compound. A solder element (308) including tin is metallurgically attached to the alloy layer across the pad area. No fraction of the original thin nickel layer is left after the reflow process. Copper/tin alloys help to improve the drop test performance, nickel/copper/tin alloys help to improve the life test performance.Type: ApplicationFiled: August 11, 2005Publication date: February 15, 2007Inventor: Kazuaki Ano
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Patent number: 7154166Abstract: A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder balls and the second openings configured to accommodate circuit chips. A copper foil is laminated on the adhesive layer, and the portion of this copper foil in the second openings is mechanically shaped into a position coplanar with the second surface, whereby it becomes useable as a chip mount pad, exposed after encapsulation for low resistance heat dissipation. The circuit chips are mounted by means of a thermally conductive material on each of the chip mount pads. Encapsulating material surrounds the mounted chips in low profile. For ball grid array devices, solder balls are attached to the copper foil exposed by the first openings in the tape.Type: GrantFiled: August 15, 2001Date of Patent: December 26, 2006Assignee: Texas Instruments IncorporatedInventor: Kazuaki Ano
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Publication number: 20060157831Abstract: A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder balls and the second openings configured to accommodate circuit chips. A copper foil is laminated on the adhesive layer, and the portion of this copper foil in the second openings is mechanically shaped into a position coplanar with the second surface, whereby it becomes useable as a chip mount pad, exposed after encapsulation for low resistance heat dissipation. The circuit chips are mounted by means of a thermally conductive material on each of the chip mount pads. Encapsulating material surrounds the mounted chips in low profile. For ball grid array devices, solder balls are attached to the copper foil exposed by the first openings in the tape.Type: ApplicationFiled: March 22, 2006Publication date: July 20, 2006Inventor: Kazuaki Ano