Abstract: Disclosed herein is a process for assembling an integrated circuit, as well as the assembly resulting from the process, employing a surface treatment of bondpad surfaces. In one aspect, a method of assembling an integrated circuit includes providing a substrate having electrical terminals on a first side of the substrate and a bondpad on a second side of the substrate opposing the first side. In this embodiment, the bondpad is electrically coupled to at least one of the terminals on the first side. In addition, the method includes mounting an integrated circuit chip to the first side of the substrate, where the integrated circuit component has a lead adapted to be wire-bonded to the terminal. The method further includes removing oxidation from the bondpad, where the bondpad is adapted to be metallurgically bonded to a trace on a printed circuit board. Moreover, this embodiment of the method includes metallurgically bonding the bondpad to the trace.

Abstract: The objective of this invention is to provide a type of substrate for carrying a semiconductor chip that can increase the arrangement density of lands, and a type of semiconductor device that makes use of said substrate for carrying a semiconductor chip. Constitution: The conductor pattern on insulating substrate 102 contains lands 130 that are respectively connected to electrode pads 120 of semiconductor chip 100 via conductor wires 110. Each land 130 of conductor pattern 110 as capillary tool contact portion 202 where the capillary tool makes contact during bonding, and wire contact portion 204 that allows contact of conductor wire 110. The portion of wire contact portion 204 on the side toward capillary tool contact portion 202 becomes constricted portion 200. Lands 130 are positioned such that constricted portion 200 and capillary tool contact portion 202 of adjacent lands 130 are arranged facing each other.

Abstract: Disclosed herein is a process for assembling an integrated circuit, as well as the assembly resulting from the process, employing a surface treatment of bondpad surfaces. In one aspect, a method of assembling an integrated circuit includes providing a substrate having electrical terminals on a first side of the substrate and a bondpad on a second side of the substrate opposing the first side. In this embodiment, the bondpad is electrically coupled to at least one of the terminals on the first side. In addition, the method includes mounting an integrated circuit chip to the first side of the substrate, where the integrated circuit component has a lead adapted to be wire-bonded to the terminal. The method further includes removing oxidation from the bondpad, where the bondpad is adapted to be metallurgically bonded to a trace on a printed circuit board. Moreover, this embodiment of the method includes metallurgically bonding the bondpad to the trace.

Abstract: A method for applying solder paste to a circuit board includes covering a circuit board with a first stencil. The first stencil includes a first stencil hole. Solder paste is applied to a first area of the circuit board through the first stencil. The circuit board is then covered by a second stencil. The second stencil includes a second stencil hole and a void enclosure. The void enclosure covers the first area and prevents the second stencil from touching the first area. Solder paste is applied to a second area of the circuit board through the second stencil. The second stencil hole has a width greater than the first stencil hole in order to obtain different solder widths on the circuit board to accommodate components of different pitch sizes.

Abstract: An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded to said contact pad. This interconnect includes a wire (304) attached to the pad by ball bonding (305), a loop (306) in the wire closed by bonding the wire to itself (307) near the ball, and a portion (307) of the remainder of the wire extended approximately parallel to the surface. The interconnect can be confined to a space (308) equal to or less than three ball heights from the surface.

Abstract: Disclosed are high reliability solder joints and methods for manufacturing the same. Methods are disclosed forming a solder joint (26) in an electronic assembly (10) having one or more copper connection sites (16) including steps for applying a nickel layer (22) with a carefully controlled thickness to the copper connection site (16), and applying a diffusion layer (24) to the thin nickel layer (22). Further steps are disclosed for positioning lead-free solder (18) adjacent to the diffusion layer (24), and for reflowing the solder (18) to form a highly reliable solder joint (26). Also disclosed is a solder joint (26) for use in a semiconductor apparatus (10) having at least one copper connection site (16). The solder joint (26) includes a thin intermetallic compound layer (28) bonded to the copper connection site (16) and lead-free solder (18) encapsulating the thin intermetallic compound layer (28).

Abstract: An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded to said contact pad. This interconnect includes a wire (304) attached to the pad by ball bonding (305), a loop (306) in the wire closed by bonding the wire to itself (307) near the ball, and a portion (307) of the remainder of the wire extended approximately parallel to the surface. The interconnect can be confined to a space (308) equal to or less than three ball heights from the surface.

Abstract: An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded to said contact pad. This interconnect includes a wire (304) attached to the pad by ball bonding (305), a loop (306) in the wire closed by bonding the wire to itself (307) near the ball, and a portion (307) of the remainder of the wire extended approximately parallel to the surface. The interconnect can be confined to a space (308) equal to or less than three ball heights from the surface.

Abstract: An air release molding system that injects high-pressure air into the die during the mold die release to eradicate mold resin sticking onto the mold die during the die release process.

Abstract: A semiconductor device (100) has a semiconductor chip (102) mounted on a tape carrier (104). Tape carrier (104) of thickness t has a plurality of via holes (118) of inner diameter Dv penetrating the tape carrier (104). Solder balls (114) having outer diameter Db are attached through the via holes (118) to serve as external connection terminals for the semiconductor chip (102). Specific dimensional relationships are established among thickness t of tape carrier (104), inner diameter Dv of via holes (118) and outer diameter Db of solder balls (114) in order to improve connection reliability by reducing poor connections of solder balls (114).

Abstract: The present invention provides a multichip arrangement and method of arranging multiple chips including at least a first chip (10) and second chip (30). The first chip (10) having opposing top and bottom surfaces in which bonding pads are located on a perimeter of the top surface. The bonding pads are operable for bonding bond wires for coupling the multichip arrangement to a circuit board (40), for example. The second chip (30) also has opposing top and bottom surfaces with bonding pads located on a perimeter of the top surface. In one embodiment an attach layer (220) having an area equal to an area of the second chip bottom surface is applied to the second chip bottom surface. The second chip (30) is coupled to the first chip (10) via the attach layer (220). The attach layer (220) has a thickness to provide electrical disconnection of the first chip wire bonds and the second chip (30).

Abstract: The objective of this invention is to provide a type of substrate for carrying a semiconductor chip that can increase the arrangement density of lands, and a type of semiconductor device that makes use of said substrate for carrying a semiconductor chip. Constitution: The conductor pattern on insulating substrate 102 contains lands 130 that are respectively connected to electrode pads 120 of semiconductor chip 100 via conductor wires 110. Each land 130 of conductor pattern 110 as capillary tool contact portion 202 where the capillary tool makes contact during bonding, and wire contact portion 204 that allows contact of conductor wire 110. The portion of wire contact portion 204 on the side toward capillary tool contact portion 202 becomes constricted portion 200. Lands 130 are positioned such that constricted portion 200 and capillary tool contact portion 202 of adjacent lands 130 are arranged facing each other.

Abstract: A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder balls and the second openings configured to accommodate circuit chips. A copper foil is laminated on the adhesive layer, and the portion of this copper foil in the second openings is mechanically shaped into a position coplanar with the second surface, whereby it becomes useable as a chip mount pad, exposed after encapsulation for low resistance heat dissipation. The circuit chips are mounted by means of a thermally conductive material on each of the chip mount pads. Encapsulating material surrounds the mounted chips in low profile. For ball grid array devices, solder balls are attached to the copper foil exposed by the first openings in the tape.

Abstract: To completely suppress or minimize the voids formed between the insulating substrate and the IC chip in order to prevent the problems of separation and cracking of the chip caused by the aforementioned voids. The present invention is preferably adopted for the Chip Six Package type package or other package types equipped with solder bumps or other external connecting terminals directly beneath the IC chip. For insulating substrate (3), on its chip-carrying surface, there is pattern element (6) in the region beneath the IC chip and free of conductor pattern elements (4) in addition to conductor pattern element (4) for forming electrical connection between the electrode pads and the external connecting terminals of the chip. Said pattern element (6) divides said region into plural small regions A. IC chip (2) is bonded through die paste on insulating substrate (3) such that an end of conductor pattern element (4), pattern element (6) and divided small regions A are covered.

Abstract: The goal of the present invention is in the manufacture of BGA type semiconductor IC packages, to obviate the processing step in which the through-holes in the insulating substrate are filled with solder paste, and to reduce the thermal stress at the bonding portion of the solder balls.This goal is achieved through the following. Through-holes (2a) are formed on insulating substrate (2) at positions corresponding to the positions where the solder balls are formed. On the surface of the insulating substrate where chip (3) is carried, conductor pattern (6) is formed, with the end [of each portion] of the conductor pattern positioned above through-hole (2a). The region of the aforementioned conductor pattern on each through-hole has portion (6d) protruding into the through-hole. Solder ball (7) is moved and carried on each through-hole to make contact with said bump portion (6d). In this state, the solder balls are melted and bump portions (6d) are directly bonded on solder balls (7).