Abstract: The present invention provides a communication semiconductor integrated circuit device equipped with a high-frequency power amplifier circuit including a gain control amplifier and a bias circuit which supplies such a bias current as to linearly change the gain of the gain control amplifier, and a wireless communication system using the same. A bias current generating circuit which supplies a bias current to a linear amplifier that constitutes the communication high-frequency power amplifier circuit, comprises a plurality of variable current sources respectively different in current value and start level. These variable current sources are controlled according to an input control voltage and thereby combine their currents into a bias current. The combined bias current changes exponentially with respect to the input control voltage.

Abstract: The present invention provides a communication semiconductor integrated circuit device equipped with a high-frequency power amplifier circuit including a gain control amplifier and a bias circuit which supplies such a bias current as to linearly change the gain of the gain control amplifier, and a wireless communication system using the same. A bias current generating circuit which supplies a bias current to a linear amplifier that constitutes the communication high-frequency power amplifier circuit, comprises a plurality of variable current sources respectively different in current value and start level. These variable current sources are controlled according to an input control voltage and thereby combine their currents into a bias current. The combined bias current changes exponentially with respect to the input control voltage.

Abstract: A wireless LAN system has auto gain control with no work load applied to its baseband processing block. When the wireless LAN system gets ready to receive a signal, the gain control circuit switches between the receiving antennas. The gain control circuit sets gain setting value time divisional data according to the level of a received signal to roughly control the gain to be set in the LAN and the gain to be set in two programmable gain amplifiers.

Abstract: In a direct conversion receiver, to cancel a DC offset generated in the baseband processing block, negative feedback arrangements comprising a gain control amplifier and a low-pass filter are respectively attached to the I and Q signal branches of the baseband block following mixer outputs. The gain control amplifier in each negative feedback circuit is gain adjusted so that the product G-B of the gain G of a primary gain control amplifier and its own gain B will be constant and thereby the DC offset is cancelled. This DC offset cancellation can be applied in a continuous receiving system with no intermittent time during a receiving operation. Capacitance elements located off-chip can be reduced to those to be used only in the low-pass filters in the negative feedback circuits, whereas many off-chip capacitance elements have been required to be inserted between each stage of gain control amplifiers in conventional baseband chains.

Abstract: In a direct conversion receiver, to cancel a DC offset generated in the baseband processing block, negative feedback arrangements comprising a gain control amplifier and a low-pass filter are respectively attached to the I and Q signal branches of the baseband block following mixer outputs. The gain control amplifier in each negative feedback circuit is gain adjusted so that the product G·B of the gain G of a primary gain control amplifier and its own gain B will be constant and thereby the DC offset is cancelled. This DC offset cancellation can be applied in a continuous receiving system with no intermittent time during a receiving operation. Capacitance elements located off-chip can be reduced to those to be used only in the low-pass filters in the negative feedback circuits, whereas many off-chip capacitance elements have been required to be inserted between each stage of gain control amplifiers in conventional baseband chains.

Abstract: A communication semiconductor integrated circuit device is capable of transmission in two or more different modulation modes and outputting transmission signals with less distortion. The communication semiconductor integrated circuit device comprises a gain variable amplification circuit which amplifies I-signals and Q-signals; and a mixer circuit which synthesizes the amplified I-signals and Q-signals and local oscillation signals to carry out modulation and frequency conversion. The communication semiconductor integrated circuit device is capable of transmission in two or more different modulation methods, for example, in GSM mode and EDGE mode. A low-pass filter of second or higher order is placed between the gain variable amplification circuit and the mixer circuit.

Abstract: There is provided an LC resonance type oscillation circuit with a wide frequency variable range with a small variation of Q and capable of reducing a chip size due to no external parts required, and a communication semiconductor circuit device (high-frequency IC) having the oscillation circuit. In the LC resonance type oscillation circuit, a capacitance element and a switch element are connected in parallel between both terminals of a secondary side inductance element which is placed facing an inductance element constituting the LC resonance circuit and is connected by mutual induction to the inductance element. It is designed so that an equivalent inductance increases as the capacitance element is connected between the both terminals of the secondary side inductance element in a state where the switch element is turned OFF, and that the equivalent inductance decreases as the both terminals of the secondary side inductance element are short-circuited in a state where the switch element is turned ON.

Abstract: Disclosed is a direct conversion type transmitter or transceiver circuit suitable for a mobile communication device which corresponds to broad signal output level variable width to be required by W-CDMA, which does not necessitate any high-performance low noise VCO and RF filter, capable of reducing a number of components and the cost. In the input portion of an orthogonal modulator composed of a divider, mixers, and a common load, there are provided variable attenuators. If an input signal level of the orthogonal modulator within the transmitter circuit lowers, this variable attenuator circuit is operated so as to lower the bias of the orthogonal modulator to reduce the amount of occurrence of carrier leak, and to prevent the signal during low output level and carrier leak ratio from being deteriorated.

Abstract: A wireless communication receiver that is able to lessen the effect of noise that accompanies gain change by programmable gain amplifiers. The receiver includes an AGC controller which controls the timing at which the programmable gain amplifiers make gain change, using a terminal counter and a sequencer. The receiver prevents gain change noise signals during the reception of control signals and other signals that are susceptible to noise. By the timing control feature, the programmable gain amplifiers make gain change while reducing noise impact.

Abstract: As the gain control amplifiers for amplifying the reception signal, the step amplifiers are used. Two sets of these step amplifiers are provided and are then controlled to be used alternately. When switching of the gain occurs, after the gain is switched with the step amplifier not operated and offset is cancelled, the amplifier to which the reception signal is inputted is switched. Accordingly, the step amplifier can be used as the gain control amplifier for amplifying the reception signal to provide almost constant power consumption even when the gain is changed depending on the intensity of reception signal in the semiconductor integrated circuit device for communication to form a wireless communication system of dual-mode or more modes including the W-CDMA system. As a result, the operation life of battery, namely, the reception waiting period and communication period by single charging process can be expanded.

Abstract: There are provided a transmitter and a wireless communication terminal apparatus using the same for solving a problem of undesired spurs due to harmonics of an output signal of a frequency synthesizer, and further solving a problem of the undesired spurs occurring when the harmonics of an output signal of a crystal oscillator are mixed into a VCO to facilitate to design a circuit or a mounting substrate. The transmitter has a relationship between an output frequency of a PLL frequency conversion circuit (5) and output frequencies of frequency synthesizers (1, 2) stored therein, and the output frequencies of the frequency synthesizers (1, 2) input into the PLL frequency conversion circuit (5) are controlled on the basis of the relationship so that the undesired spurs are suppressed.

Abstract: As the gain control amplifiers for amplifying the reception signal, the step amplifiers are used. Two sets of these step amplifiers are provided and are then controlled to be used alternately. When switching of the gain occurs, after the gain is switched with the step amplifier not operated and offset is cancelled, the amplifier to which the reception signal is inputted is switched. Accordingly, the step amplifier can be used as the gain control amplifier for amplifying the reception signal to provide almost constant power consumption even when the gain is changed depending on the intensity of reception signal in the semiconductor integrated circuit device for communication to form a wireless communication system of dual-mode or more modes including the W-CDMA system. As a result, the operation life of battery, namely, the reception waiting period and communication period by single charging process can be expanded.

Abstract: Disclosed is a direct conversion type transmitter or transceiver circuit suitable for a mobile communication device which corresponds to broad signal output level variable width to be required by W-CDMA, which does not necessitate any high-performance low noise VCO and RF filter, capable of reducing a number of components and the cost. In the input portion of an orthogonal modulator composed of a divider, mixers, and a common load, there are provided variable attenuators. If an input signal level of the orthogonal modulator within the transmitter circuit lowers, this variable attenuator circuit is operated so as to lower the bias of the orthogonal modulator to reduce the amount of occurrence of carrier leak, and to prevent the signal during low output level and carrier leak ratio from being deteriorated.

Abstract: A wireless communication receiver that is able to lessen the effect of noise that accompanies gain change by programmable gain amplifiers. The receiver includes an AGC controller which controls the timing at which the programmable gain amplifiers make gain change, using a terminal counter and a sequencer. The receiver prevents gain change noise signals during the reception of control signals and other signals that are susceptible to noise. By the timing control feature, the programmable gain amplifiers make gain change while reducing noise impact.

Abstract: The dynamic range is changed by switching a current applied to an amplifying circuit to obtain the minimum ICP required to keep linearity with the number of multiplexes even when the number of multiplexes of data is changed by switching the operation current of the amplifying circuits of the transmission system and also supplying the information about number of multiplexes of data to be transmitted to the amplifying circuits of the transmission system from the baseband circuit. Thereby, the signal can be transmitted without distortion even when the number of multiplexes increases and the current of the amplifying circuit may be reduced when the number of multiplexes is small in order to reduce the current consumption in the communication semiconductor integrated circuit device which can form a wireless communication system of the code division multiplex system such as W-CDMA system.

Abstract: The dynamic range is changed by switching a current applied to an amplifying circuit to obtain the minimum ICP required to keep linearity with the number of multiplexes even when the number of multiplexes of data is changed by switching the operation current of the amplifying circuits of the transmission system and also supplying the information about number of multiplexes of data to be transmitted to the amplifying circuits of the transmission system from the baseband circuit. Thereby, the signal can be transmitted without distortion even when the number of multiplexes increases and the current of the amplifying circuit may be reduced when the number of multiplexes is small in order to reduce the current consumption in the communication semiconductor integrated circuit device which can form a wireless communication system of the code division multiplex system such as W-CDMA system.

Abstract: A semiconductor integrated circuit comprising a first circuit block including an oscillation circuit considered to be a noise generator and a second circuit block including circuits considered to be easily affected by a noise generated by the oscillation circuit, being most likely led to a malfunction are created on a single semiconductor substrate with the first and second circuit blocks separated from each other. To put it more concretely, the first and second circuit blocks are respectively created in a first island area and a second island area on the surface of the semiconductor substrate. The first and second island areas are each enclosed by an insulating isolation band. A low-resistance semiconductor area is created in a base area excluding locations occupied by active elements in the first and second island areas and is connected to a stable voltage terminal.

Abstract: A direct upconversion system communication semiconductor integrated circuit includes a frequency converter circuit for up-converting a transmission signal and a notch filter located at a subsequent stage of the frequency converter circuit. The notch filter is served to cut off at least third-order harmonics of a local signal.

Abstract: In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.

Abstract: In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.