Abstract: An MIS FET has an off-set gate structure in which a gate electrode and a drain region. The drain region is formed of an n type impurity region of a high concentration and has a pn junction region provided between the drain region and the p type silicon substrate. Further, n type impurity regions of the low concentration are in contact with a part of a peripheral portion of the n type impurity regions of the high concentration. The n type impurity regions of the low concentration alleviate the concentration of the electric field near the drain region to increase the drain breakdown voltage. The pn junction region of the n type impurity region of the high concentration and the p type silicon substrate increases a junction capacitance of the entire drain region, increases a surge current discharged to the substrate side from the drain region for the surge breakdown to increase the surge withstanding amount.

Abstract: Disclosed is a structure of a semiconductor device in which an internal circuit including a memory device and a transistor having an LDD structure, and an input protection device for protecting the internal circuit are formed on one semiconductor substrate, and a method of manufacturing such a semiconductor device. The input protection device and the memory device are formed at the same time. The input protection device as well as the memory device includes source/drain regions formed of high concentration impurity regions and formed in the surface of the semiconductor substrate, and a gate electrode formed of a plurality of conductor films and formed on the surface of the semiconductor substrate between the source/drain regions.

Abstract: A single chip microcomputer as a semiconductor device comprises CMOS logic portion and a driver portion operating at a high voltage which can be connected to an external device. In the region of the CMOS logic portion, a P type well layer and an N type well layer are formed on a P type silicon substrate. An N type well layer is formed in the region constituting the driver portion. The junction depth of the N type well layer constituting the driver portion is made deeper than that of the N type well layer constituting the CMOS logic portion. A MOS transistor is formed in the region of each well layer in the CMOS logic portion. A MOS transistor whose drain breakdown voltage is increased is formed in the region of the N type well layer of the driver portion. The junction depth of the N type well layer is made deeper than that of the N type well layer constituting the CMOS logic portion at least below the drain region of this MOS transistor.

Abstract: The semiconductor device is of high break down voltage type and has a source, drain and a gate deposited therebetween on the semiconductor substrate. The gate oxide film has a thick portion and below that portion, a doped layer as a drain is provided with two layers having different impurity concentration.

Abstract: A semiconductor integrated circuit which is of entire microstructure so as to reduce a gate length as to an EPROM formed on a substrate, thereby increasing the quantity of a current flowing between a source and a drain and, on the other hand, a transistor portion other than the EPROM on the same substrate is of structure for weakening the electric field between the source region and the drain region by means of the LDD technique or the like, thereby preventing the occurrence of a breakdown in the channel caused by hot electrons.