Patents by Inventor Kazuaki Ohshima

Kazuaki Ohshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230363174
    Abstract: A ferroelectric device including a metal oxide film having favorable ferroelectricity is provided. The ferroelectric device includes a first conductor, a metal oxide film over the first conductor, and a second conductor over the metal oxide film. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.
    Type: Application
    Filed: September 9, 2021
    Publication date: November 9, 2023
    Inventors: Shunpei YAMAZAKI, Yasuhiro JINBO, Hitoshi KUNITAKE, Kazuaki OHSHIMA, Masashi OOTA, Kazuma FURUTANI, Takeshi AOKI
  • Patent number: 11600705
    Abstract: A semiconductor device in which a transistor has the characteristic of low off-state current is provided. The transistor comprises an oxide semiconductor layer having a channel region whose channel width is smaller than 70 nm. A temporal change in off-state current of the transistor over time can be represented by Formula (a2). In Formula (a2), IOFF represents the off-state current, t represents time during which the transistor is off, ? and ? are constants, ? is a constant that satisfies 0<??1, and CS is a constant that represents load capacitance of a source or a drain.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: March 7, 2023
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masashi Tsubuku, Shunpei Yamazaki, Hidetomo Kobayashi, Kazuaki Ohshima, Masashi Fujita, Toshihiko Takeuchi
  • Publication number: 20230067352
    Abstract: A semiconductor device being capable of high-speed data transmission and having a reduced circuit area is provided. The semiconductor device includes a semiconductor chip, an external terminal, and a layer including two facing surfaces. The semiconductor chip is provided on one surface side of the layer, and the external terminal is provided on the other surface side of the layer at least in a region not overlapping with the semiconductor chip. The semiconductor chip includes a first circuit including a first transistor, and the layer includes a second circuit including a second transistor. The first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the external terminal. The second transistor includes a metal oxide in a channel formation region. Note that the second circuit may be a CML circuit. In addition, an insulator may be provided above the one surface of the layer and on a side surface of the semiconductor chip.
    Type: Application
    Filed: March 1, 2021
    Publication date: March 2, 2023
    Inventors: Kazuaki OHSHIMA, Hitoshi KUNITAKE
  • Publication number: 20220352865
    Abstract: An amplifier is formed in a wiring layer. A semiconductor device includes a second layer over a first layer with a metal oxide therebetween. The first layer includes a first transistor including a first semiconductor layer containing silicon. The second layer includes an impedance matching circuit, and the impedance matching circuit includes a second transistor including a second semiconductor layer containing gallium. The first transistor forms first coupling capacitance between the first transistor and the metal oxide, and the impedance matching circuit forms second coupling capacitance between the impedance matching circuit and the metal oxide. The impedance matching circuit is electrically connected to the metal oxide through the second coupling capacitance. The metal oxide inhibits the influence of first radiation noise emitted from the impedance matching circuit on the operation of the first transistor.
    Type: Application
    Filed: October 5, 2020
    Publication date: November 3, 2022
    Inventors: Kazuaki OHSHIMA, Hitoshi KUNITAKE, Yuto YAKUBO, Takayuki IKEDA
  • Publication number: 20220320330
    Abstract: A matching circuit which can handle a plurality of frequencies is provided. The matching circuit includes a transistor and an inductor. The matching circuit uses capacitance formed between a gate and a source/drain (referred to as capacitance Cgsd below) of the transistor as a condenser. The capacitance Cgsd changes with the voltage of the gate with respect to the source (referred to as voltage Vgs below). The transistor included in the matching circuit is an OS transistor including a metal oxide in a channel formation region. The OS transistor features larger variation in capacitance Cgsd with respect to the voltage Vgs than the MOSFET that uses silicon, which enables the matching circuit to handle alternating-current signals in a wide frequency range.
    Type: Application
    Filed: May 25, 2020
    Publication date: October 6, 2022
    Inventors: Hitoshi KUNITAKE, Kazuaki OHSHIMA
  • Publication number: 20220246615
    Abstract: A semiconductor device in which temperature dependence is reduced is provided. A switched capacitor is formed using a second transistor, a third transistor, and a second capacitor. Semiconductor layers of the second transistor and the third transistor that include an oxide can reduce temperature dependence. An AC signal supplied to the gates of the second transistor and the third transistor is converted into a DC voltage through the switched capacitor. Note that the level of the DC voltage is adjusted by the levels of the voltages supplied to the back gates of the second transistor and the third transistor.
    Type: Application
    Filed: May 19, 2020
    Publication date: August 4, 2022
    Inventors: Kazuaki OHSHIMA, Hitoshi KUNITAKE, Takahiro FUKUTOME
  • Publication number: 20220216830
    Abstract: To provide a mixer and a semiconductor device which each have a small circuit area and each of which operation capability is inhibited from being decreased due to heat. The mixer includes a differential portion, a current source, a first load, an input terminal, and a first output terminal; the differential portion includes a first and a second transistor; and each of the first and the second transistors includes a metal oxide in a channel formation region. A first terminal of each of the first and the second transistors is electrically connected to the input terminal and a current source and a second terminal of the first transistor is electrically connected to a first terminal of the first load and the first output terminal.
    Type: Application
    Filed: May 20, 2020
    Publication date: July 7, 2022
    Inventors: Kazuaki OHSHIMA, Hitoshi KUNITAKE, Tatsunori INOUE
  • Publication number: 20220208794
    Abstract: A semiconductor device with a small characteristic variation due to operating temperature is provided. The semiconductor device includes an odd number of stages of inverter circuits that are circularly connected. The inverter circuit includes a first transistor and a second transistor. A gate of the first transistor is electrically connected to one of a source and a drain of the first transistor, the one of the source and the drain of the first transistor is supplied with a high power supply potential, and the other of the source and the drain of the first transistor is electrically connected to an output terminal out. A gate of the second transistor is electrically connected to an input terminal in, one of a source and a drain of the second transistor is electrically connected to the output terminal out, and the other of the source and the drain of the second transistor is supplied with a low power supply potential.
    Type: Application
    Filed: April 27, 2020
    Publication date: June 30, 2022
    Inventors: Hitoshi KUNITAKE, Kazuaki OHSHIMA, Kazuki TSUDA, Tomoaki ATSUMI
  • Publication number: 20200168710
    Abstract: A semiconductor device in which a transistor has the characteristic of low off-state current is provided. The transistor comprises an oxide semiconductor layer having a channel region whose channel width is smaller than 70 nm. A temporal change in off-state current of the transistor over time can be represented by Formula (a2). In Formula (a2), IOFF represents the off-state current, t represents time during which the transistor is off, ? and ? are constants, ? is a constant that satisfies 0<??1, and CS is a constant that represents load capacitance of a source or a drain.
    Type: Application
    Filed: January 29, 2020
    Publication date: May 28, 2020
    Inventors: Masashi TSUBUKU, Shunpei YAMAZAKI, Hidetomo KOBAYASHI, Kazuaki OHSHIMA, Masashi FUJITA, Toshihiko TAKEUCHI
  • Patent number: 10559667
    Abstract: A semiconductor device in which a transistor has the characteristic of low off-state current is provided. The transistor comprises an oxide semiconductor layer having a channel region whose channel width is smaller than 70 nm. A temporal change in off-state current of the transistor over time can be represented by Formula (a2). In Formula (a2), IOFF represents the off-state current, t represents time during which the transistor is off, ? and ? are constants, ? is a constant that satisfies 0<??1, and CS is a constant that represents load capacitance of a source or a drain.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: February 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Shunpei Yamazaki, Hidetomo Kobayashi, Kazuaki Ohshima, Masashi Fujita, Toshihiko Takeuchi
  • Patent number: 10500908
    Abstract: To provide a circuit with low power consumption, a semiconductor device with low power consumption, a highly reliable semiconductor device, a tire whose performance is controlled, a moving object whose performance is controlled, or a moving object with a high degree of safety. A tire provided with a semiconductor device is provided. The semiconductor device includes a circuit portion, an antenna, and a sensor element. The circuit portion includes a transistor. The transistor includes an oxide semiconductor. The sensor element is configured to measure the air pressure of the tire.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: December 10, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Masayuki Sakakura, Kazuaki Ohshima
  • Publication number: 20180326800
    Abstract: To provide a circuit with low power consumption, a semiconductor device with low power consumption, a highly reliable semiconductor device, a tire whose performance is controlled, a moving object whose performance is controlled, or a moving object with a high degree of safety. A tire provided with a semiconductor device is provided. The semiconductor device includes a circuit portion, an antenna, and a sensor element. The circuit portion includes a transistor. The transistor includes an oxide semiconductor. The sensor element is configured to measure the air pressure of the tire.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 15, 2018
    Inventors: Tomoaki ATSUMI, Masayuki SAKAKURA, Kazuaki OHSHIMA
  • Patent number: 10109371
    Abstract: The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 23, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Shuhei Nagatsuka, Kazuaki Ohshima
  • Patent number: 10061558
    Abstract: A device for temporarily storing data output from a register or data obtained by processing the output data, a processing method therefor, a program, and the like is provided. A circuit (hereinafter, referred to as a selective memory cell) in which a plurality of switches and a signal storing circuit are connected is provided in a data processing device. The selective memory cell can selectively store necessary data. A result of a frequently performed process is stored in the selective memory cell. A process whose result is stored can be performed by only outputting the stored data instead of performing the whole process; thus, input data does not need to be transferred, which can result in a reduction in processing time.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 28, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kazuaki Ohshima
  • Patent number: 10035386
    Abstract: To provide a circuit with low power consumption, a semiconductor device with low power consumption, a highly reliable semiconductor device, a tire whose performance is controlled, a moving object whose performance is controlled, or a moving object with a high degree of safety. A tire provided with a semiconductor device is provided. The semiconductor device includes a circuit portion, an antenna, and a sensor element. The circuit portion includes a transistor. The transistor includes an oxide semiconductor. The sensor element is configured to measure the air pressure of the tire.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 31, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Masayuki Sakakura, Kazuaki Ohshima
  • Patent number: 9960116
    Abstract: A resistor whose characteristic value can be changed without requiring a photolithography process again is provided. The resistor includes a plurality of first resistor units which is connected serially to each other and a second resistor unit which is connected in parallel to part of the first resistor units. Then, after the measurement of a semiconductor integrated circuit, the second resistor unit is electrically disconnected as necessary. The first resistor units may be either a unit including a single resistor or may be a unit including a plurality of resistors.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: May 1, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kazuaki Ohshima
  • Patent number: 9875381
    Abstract: A command sequence is restarted from the middle even when supply of power supply voltage to an internal circuit in a wireless tag is temporarily stopped (a power flicker occurs). A register or a cache memory included in a signal processing circuit in the wireless tag continues to retain data even after the supply of power supply voltage is stopped. After the power flicker occurs, the signal processing circuit in the wireless tag is returned to the state before the supply of power supply voltage is stopped and can restart signal processing. Consequently, the command sequence can be restarted from the middle.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: January 23, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuaki Ohshima, Hidetomo Kobayashi
  • Publication number: 20170338349
    Abstract: A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V0 is supplied. Change in a potential VFN of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, ? is a constant with a unit of time, and ? is a constant greater than or equal to 0.4 and less than or equal to 0.6.
    Type: Application
    Filed: May 3, 2017
    Publication date: November 23, 2017
    Inventors: Masashi TSUBUKU, Kazuaki OHSHIMA, Masashi FUJITA, Daigo SHIMADA, Tsutomu MURAKAWA
  • Patent number: 9818750
    Abstract: Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: November 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuaki Ohshima, Kiyoshi Kato, Tomoaki Atsumi
  • Patent number: 9741400
    Abstract: A semiconductor device or a memory device with a reduced area, a large storage capacity, a high-speed operation, or low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, a first wiring, a second wiring, a sense amplifier circuit, a decoder, a step-up circuit, a level shifter, and a buffer circuit. The first wiring is electrically connected to the buffer circuit and a second gate electrode of the first transistor. The second wiring is electrically connected to the sense amplifier circuit and the drain electrode of the second transistor. The capacitor is electrically connected to the drain electrode of the first transistor and the source electrode of the second transistor.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: August 22, 2017
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Shuhei Nagatsuka, Tomokazu Yokoi, Naoaki Tsutsui, Kazuaki Ohshima, Tatsuya Onuki