Patents by Inventor Kazuaki Ohshima

Kazuaki Ohshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9735179
    Abstract: A semiconductor circuit capable of controlling and holding the threshold voltage of a transistor at an optimal level and a driving method thereof are disclosed. A storage device, a display device, or an electronic device including the semiconductor circuit is also provided. The semiconductor circuit comprises a diode and a first capacitor provided in a node to which a transistor to be controlled is connected through its back gate. This structure allows the application of desired voltage to the back gate so that the threshold voltage of the transistor is controlled at an optimal level and can be held for a long time. A second capacitor connected in parallel with the diode is optionally provided so that the voltage of the node can be changed temporarily.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: August 15, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Endo, Kazuaki Ohshima
  • Publication number: 20170186749
    Abstract: Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 29, 2017
    Inventors: Kazuaki OHSHIMA, Kiyoshi KATO, Tomoaki ATSUMI
  • Publication number: 20170178752
    Abstract: The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 22, 2017
    Inventors: Tomoaki ATSUMI, Shuhei NAGATSUKA, Kazuaki OHSHIMA
  • Publication number: 20170177300
    Abstract: A device for temporarily storing data output from a register or data obtained by processing the output data, a processing method therefor, a program, and the like is provided. A circuit (hereinafter, referred to as a selective memory cell) in which a plurality of switches and a signal storing circuit are connected is provided in a data processing device. The selective memory cell can selectively store necessary data. A result of a frequently performed process is stored in the selective memory cell. A process whose result is stored can be performed by only outputting the stored data instead of performing the whole process; thus, input data does not need to be transferred, which can result in a reduction in processing time.
    Type: Application
    Filed: March 1, 2017
    Publication date: June 22, 2017
    Inventor: Kazuaki OHSHIMA
  • Publication number: 20170133064
    Abstract: A semiconductor device or a memory device with a reduced area, a large storage capacity, a high-speed operation, or low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, a first wiring, a second wiring, a sense amplifier circuit, a decoder, a step-up circuit, a level shifter, and a buffer circuit. The first wiring is electrically connected to the buffer circuit and a second gate electrode of the first transistor. The second wiring is electrically connected to the sense amplifier circuit and the drain electrode of the second transistor. The capacitor is electrically connected to the drain electrode of the first transistor and the source electrode of the second transistor.
    Type: Application
    Filed: November 2, 2016
    Publication date: May 11, 2017
    Inventors: Shuhei NAGATSUKA, Tomokazu YOKOI, Naoaki TSUTSUI, Kazuaki OHSHIMA, Tatsuya ONUKI
  • Patent number: 9647132
    Abstract: A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V0 is supplied. Change in a potential VFN of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, ? is a constant with a unit of time, and ? is a constant greater than or equal to 0.4 and less than or equal to 0.6.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: May 9, 2017
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Masashi Tsubuku, Kazuaki Ohshima, Masashi Fujita, Daigo Shimada, Tsutomu Murakawa
  • Patent number: 9612795
    Abstract: A device for temporarily storing data output from a register or data obtained by processing the output data, a processing method therefor, a program, and the like is provided. A circuit (hereinafter, referred to as a selective memory cell) in which a plurality of switches and a signal storing circuit are connected is provided in a data processing device. The selective memory cell can selectively store necessary data. A result of a frequently performed process is stored in the selective memory cell. A process whose result is stored can be performed by only outputting the stored data instead of performing the whole process; thus, input data does not need to be transferred, which can result in a reduction in processing time.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: April 4, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kazuaki Ohshima
  • Publication number: 20170061173
    Abstract: A command sequence is restarted from the middle even when supply of power supply voltage to an internal circuit in a wireless tag is temporarily stopped (a power flicker occurs). A register or a cache memory included in a signal processing circuit in the wireless tag continues to retain data even after the supply of power supply voltage is stopped. After the power flicker occurs, the signal processing circuit in the wireless tag is returned to the state before the supply of power supply voltage is stopped and can restart signal processing. Consequently, the command sequence can be restarted from the middle.
    Type: Application
    Filed: November 3, 2016
    Publication date: March 2, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuaki Ohshima, Hidetomo KOBAYASHI
  • Patent number: 9570445
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other of the source and the drain of the first transistor, and the other is connected to one of a source and a drain of the fourth transistor. The other of the source and the drain of the fourth transistor is connected to a wiring supplying second potential lower than the first potential. An oxide semiconductor material is used in channel formation regions of the third transistor and the fourth transistor.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: February 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kazuaki Ohshima
  • Patent number: 9536627
    Abstract: The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: January 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Shuhei Nagatsuka, Kazuaki Ohshima
  • Publication number: 20160332493
    Abstract: To provide a circuit with low power consumption, a semiconductor device with low power consumption, a highly reliable semiconductor device, a tire whose performance is controlled, a moving object whose performance is controlled, or a moving object with a high degree of safety. A tire provided with a semiconductor device is provided. The semiconductor device includes a circuit portion, an antenna, and a sensor element. The circuit portion includes a transistor. The transistor includes an oxide semiconductor. The sensor element is configured to measure the air pressure of the tire.
    Type: Application
    Filed: May 9, 2016
    Publication date: November 17, 2016
    Inventors: Tomoaki ATSUMI, Masayuki SAKAKURA, Kazuaki OHSHIMA
  • Patent number: 9489830
    Abstract: A command sequence is restarted from the middle even when supply of power supply voltage to an internal circuit in a wireless tag is temporarily stopped (a power flicker occurs). A register or a cache memory included in a signal processing circuit in the wireless tag continues to retain data even after the supply of power supply voltage is stopped. After the power flicker occurs, the signal processing circuit in the wireless tag is returned to the state before the supply of power supply voltage is stopped and can restart signal processing. Consequently, the command sequence can be restarted from the middle.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: November 8, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuaki Ohshima, Hidetomo Kobayashi
  • Publication number: 20160293276
    Abstract: The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.
    Type: Application
    Filed: March 28, 2016
    Publication date: October 6, 2016
    Inventors: Tomoaki ATSUMI, Shuhei NAGATSUKA, Kazuaki OHSHIMA
  • Publication number: 20160225772
    Abstract: A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V0 is supplied. Change in a potential VFN of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, ? is a constant with a unit of time, and ? is a constant greater than or equal to 0.4 and less than or equal to 0.6.
    Type: Application
    Filed: January 27, 2016
    Publication date: August 4, 2016
    Inventors: Masashi TSUBUKU, Kazuaki OHSHIMA, Masashi FUJITA, Daigo SHIMADA, Tsutomu MURAKAWA
  • Patent number: 9336845
    Abstract: A semiconductor device capable of assessing and rewriting data at a desired timing is provided. A semiconductor device includes a register circuit, a bit line, and a data line. The register circuit includes a flip-flop circuit, a selection circuit, and a nonvolatile memory circuit electrically connected to the flip-flop circuit through the selection circuit. The data line is electrically connected to the flip-flop circuit. The bit line is electrically connected to the nonvolatile memory circuit through the selection circuit. The selection circuit selectively stores data based on a potential of the data line or a potential of the bit line in the nonvolatile memory circuit.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: May 10, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuaki Ohshima, Hidetomo Kobayashi
  • Publication number: 20160054362
    Abstract: A current measurement method with which an extremely low current can be measured is provided. In the method, a charge written to a first terminal of a capacitor through a transistor under test is retained, data on the correspondence between a potential V of the first terminal of the capacitor and Time t is generated, and a stretched exponential function represented by Formula (a1) is fitted to the data to determine parameters of Formula (a1). The derivative of Formula (a1) with respect to time gives a stretched exponential function describing an off-state current of the transistor under test. The potential of the first terminal of the capacitor is measured using an on-state current of a transistor whose gate is connected to the first terminal of the capacitor.
    Type: Application
    Filed: August 20, 2015
    Publication date: February 25, 2016
    Inventors: Masashi TSUBUKU, Shunpei YAMAZAKI, Hidetomo KOBAYASHI, Kazuaki OHSHIMA, Masashi FUJITA, Toshihiko TAKEUCHI
  • Publication number: 20150171117
    Abstract: A semiconductor circuit capable of controlling and holding the threshold voltage of a transistor at an optimal level and a driving method thereof are disclosed. A storage device, a display device, or an electronic device including the semiconductor circuit is also provided. The semiconductor circuit comprises a diode and a first capacitor provided in a node to which a transistor to be controlled is connected through its back gate. This structure allows the application of desired voltage to the back gate so that the threshold voltage of the transistor is controlled at an optimal level and can be held for a long time. A second capacitor connected in parallel with the diode is optionally provided so that the voltage of the node can be changed temporarily.
    Type: Application
    Filed: February 26, 2015
    Publication date: June 18, 2015
    Inventors: Masami ENDO, Kazuaki OHSHIMA
  • Patent number: 9059704
    Abstract: An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: June 16, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiichi Yoneda, Jun Koyama, Yutaka Shionoiri, Masami Endo, Hiroki Dembo, Tatsuji Nishijima, Hidetomo Kobayashi, Kazuaki Ohshima
  • Patent number: 9024317
    Abstract: A semiconductor circuit capable of controlling and holding the threshold voltage of a transistor at an optimal level and a driving method thereof are disclosed. A storage device, a display device, or an electronic device including the semiconductor circuit is also provided. The semiconductor circuit comprises a diode and a first capacitor provided in a node to which a transistor to be controlled is connected through its back gate. This structure allows the application of desired voltage to the back gate so that the threshold voltage of the transistor is controlled at an optimal level and can be held for a long time. A second capacitor connected in parallel with the diode is optionally provided so that the voltage of the node can be changed temporarily.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: May 5, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Endo, Kazuaki Ohshima
  • Publication number: 20140332805
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other of the source and the drain of the first transistor, and the other is connected to one of a source and a drain of the fourth transistor. The other of the source and the drain of the fourth transistor is connected to a wiring supplying second potential lower than the first potential. An oxide semiconductor material is used in channel formation regions of the third transistor and the fourth transistor.
    Type: Application
    Filed: July 24, 2014
    Publication date: November 13, 2014
    Inventor: Kazuaki OHSHIMA