Abstract: A wireless communication apparatus includes a signal terminal which receives a transmitting signal, N antenna elements, where N is an integer greater than or equal to 2, a first amplifier including first input and output terminals, and N second amplifiers including N second input and output terminals coupled to the N antenna elements, respectively. The first amplifier amplifies the transmitting signal received from the signal terminal via the first input terminal with a gain which is weighted and adjustable according to a first weight. The N second amplifiers amplify the amplified transmitting signal received from the second output terminal via the N second input terminals with gains which are weighted and adjustable according to N second weights. The amplified transmitting signal, amplified by the N second amplifiers, is output to the N antenna elements via the N second output terminals.

Abstract: A wireless communication apparatus includes a signal terminal which receives a transmitting signal, N antenna elements, where N is an integer greater than or equal to 2, a first amplifier including first input and output terminals, and N second amplifiers including N second input and output terminals coupled to the N antenna elements, respectively. The first amplifier amplifies the transmitting signal received from the signal terminal via the first input terminal with a gain which is weighted and adjustable according to a first weight. The N second amplifiers amplify the amplified transmitting signal received from the second output terminal via the N second input terminals with gains which are weighted and adjustable according to N second weights. The amplified transmitting signal, amplified by the N second amplifiers, is output to the N antenna elements via the N second output terminals.

Abstract: A delay locked loop circuit includes a first delay circuit that includes a plurality of first delay devices and a plurality of second delay devices, the plurality of first delay devices and the plurality of second delay devices are coupled in series with each other, a second delay circuit that includes a plurality of third delay devices equal in number and identical in configuration to the plurality of second delay devices, the plurality of third delay devices are coupled in series with each other, a phase comparator that outputs a phase difference between a first delayed clock output from the first delay circuit and a second delayed clock output from the second delay circuit, a first control circuit that outputs a first control signal that controls a time, and a second control circuit that outputs a second control signal.

Abstract: An OTA circuit includes a first input stage that includes a first pair of transistors having sources coupled to a reference potential and converts a differential input voltage input to gates of the first pair of transistors into a first control current, a second input stage that includes a second pair of transistors having sources coupled to the reference potential and converts the differential input voltage input to gates of the second pair of transistors into a second control current, a first output circuit that generates one output current out of the differential output currents in accordance with the first control current, and a second output circuit that generates the other output current out of the differential output currents in accordance with the second control current.

Abstract: A pulse position modulation circuit includes a delay path that includes a plurality of delay devices coupled in series with each other, a clock being passed through the plurality of delay devices, and a switching circuit that changes a time by which the clock is delayed in each of the plurality of delay devices according to input data.

Abstract: An OTA circuit includes a first input stage that includes a first pair of transistors having sources coupled to a reference potential and converts a differential input voltage input to gates of the first pair of transistors into a first control current, a second input stage that includes a second pair of transistors having sources coupled to the reference potential and converts the differential input voltage input to gates of the second pair of transistors into a second control current, a first output circuit that generates one output current out of the differential output currents in accordance with the first control current, and a second output circuit that generates the other output current out of the differential output currents in accordance with the second control current.

Abstract: A power source circuit includes a linear regulator including: an amplifier configured to amplify an envelope signal for representing an envelope of an input signal input into a power amplifier, and an output stage including transistors, configured to output power output to be supplied to the power amplifier in accordance with amplified output of the amplifier; a monitor circuit configured to monitor the envelope signal; and a switched-capacitor circuit configured to generate a power source voltage higher than a voltage of the power output based on a monitoring result of the monitor circuit, wherein the switched-capacitor circuit does not supply the power source voltage to the amplifier, but supplies the power source voltage to the output stage.

Abstract: A power amplifier circuit includes unit amplifiers (unit PAs) whose output terminals are connected to one another, among which a number of unit PAs to be operated is controlled by an amplitude signal indicative of an amplitude of an input signal, and which output output signals based on a phase signal indicative of a phase of the input signal and an output current controller which controls an output current of each of the unit PAs. Each unit PA includes a first transistor and a second transistor connected in series between the output terminal and a ground. The first transistor receives the phase signal at a gate. The second transistor receives at a gate a control signal generated by the output current controller and determines the output current flowing to the output terminal on the basis of the control signal.

Abstract: An electronic apparatus includes: a load; a first battery; a second battery; and a power supply control circuit configured to couple the first battery and the second battery to the load, wherein the power supply control circuit includes: a first switch including one end coupled to the first battery and the other end coupled to the load; a second switch including one end coupled to the second battery and the other end coupled to the load; and a first comparison circuit including a first input terminal coupled to an output terminal of the first battery and a second input terminal coupled to a threshold voltage and configured to control the first switch and the second switch based on a comparison result of an output voltage of the first battery and the threshold voltage and output a first battery selection signal indicating whether the first battery powers the load.

Abstract: A communication device includes a receiving circuit and a start-up time adjustment circuit configured to transmit, to the receiving circuit, a start signal that instructs a change from a sleep state to an active state, wherein the start-up time adjustment circuit is configured to transmit, to the receiving circuit, a first start signal that instructs a change from the sleep state to the active state at a first time earlier than a second time when a first signal reaches the communication device, measure a first time difference between the second time and the first time, determine, based on the first time difference, a third time when the receiving circuit is changed from the active state to the sleep state, and transmit a second start signal that instructs a change from the sleep state to the active state to the receiving circuit at the third time.

Abstract: A power amplifier circuit includes unit amplifiers (unit PAs) whose output terminals are connected to one another, among which a number of unit PAs to be operated is controlled by an amplitude signal indicative of an amplitude of an input signal, and which output output signals based on a phase signal indicative of a phase of the input signal and an output current controller which controls an output current of each of the unit PAs. Each unit PA includes a first transistor and a second transistor connected in series between the output terminal and a ground. The first transistor receives the phase signal at a gate. The second transistor receives at a gate a control signal generated by the output current controller and determines the output current flowing to the output terminal on the basis of the control signal.

Abstract: A power supply device includes a linear regulator including an output stage amplifier, a current sensing circuit, and a switching regulator. The current sensing circuit detects an output current of the linear regulator, and is disposed in parallel with the output stage amplifier, in a configuration corresponding to the output stage amplifier. The switching regulator operates in accordance with an output signal of the current sensing circuit. The linear regulator and the switching regulator operate in collaboration with each other to generate an output voltage at an output node.

Abstract: A processor activates a first monitoring process for initializing a timer and a second monitoring process with higher priority than the first monitoring process. The processor executes the second monitoring process to monitor whether the first monitoring process has been executed. When determining that the first monitoring process has not been executed, the processor executing the second monitoring process determines whether the load state of the processor satisfies prescribed conditions. If the load state satisfies the prescribed conditions, the processor executing the second monitoring process initializes the timer.

Abstract: A differential amplification circuit includes: a first input node; a second input node; a first output node; a second output node; a first transistor having a gate coupled to the first input node and a source coupled to a first node; a second transistor having a gate coupled to the second input node; a third transistor having a drain coupled to a drain of the first transistor; a fourth transistor having a gate coupled to a gate of the third transistor; a first resistor; a second resistor; a fifth transistor having a gate coupled to the drain of the first transistor; a sixth transistor having a gate coupled to the drain of the second transistor; a seventh transistor having a source coupled to the first node; an eighth transistor having a gate coupled to a gate of the seventh transistor; a third resistor; and a fourth resistor.

Abstract: A device includes: a nonvolatile memory configured to store data; a volatile memory configured to store the data read out from the nonvolatile memory; a processor configured to perform processing using the data stored in the volatile memory; and a measurement circuit configured to measure standby power of the volatile memory when the power of the volatile memory is turned on, wherein the processor is configured to control, based on a measurement result outputted from the measurement circuit, power supply to the volatile memory while the processor is to be intermittently operated.

Abstract: A communication device includes a receiving circuit and a start-up time adjustment circuit configured to transmit, to the receiving circuit, a start signal that instructs a change from a sleep state to an active state, wherein the start-up time adjustment circuit is configured to transmit, to the receiving circuit, a first start signal that instructs a change from the sleep state to the active state at a first time earlier than a second time when a first signal reaches the communication device, measure a first time difference between the second time and the first time, determine, based on the first time difference, a third time when the receiving circuit is changed from the active state to the sleep state, and transmit a second start signal that instructs a change from the sleep state to the active state to the receiving circuit at the third time.

Abstract: A power on reset circuit including: a startup circuit keeping an operation signal in an operating state during a power supply rises; a bias circuit keeping the operation signal in the operating state; a BGR circuit being activated during the operating state, and outputting a fixed voltage after a predetermined time elapses; a power supply divided voltage generation circuit outputting a reference voltage; an activation detection circuit generating a control signal which becomes inactive when a power supply rises and becomes active when the fixed voltage reaches a predetermined level; a comparator circuit outputting a power on signal and detecting as the power on signal when the reference voltage is greater than the fixed voltage; and a switch turning on and fixing an output of the comparator circuit to an inactive logical value while the control signal is inactive, and turning off while the control signal is active.

Abstract: A signal generation circuit includes a limiter and a mixer. The limiter receives an input signal, allows the input signal to be off a scale at a limit voltage, and generates a phase signal indicating a phase component of the input signal. The mixer receives the input signal and the phase signal, and generates an amplitude signal indicating an amplitude component of the input signal.

Abstract: A differential amplification circuit includes: a first input node; a second input node; a first output node; a second output node; a first transistor having a gate coupled to the first input node and a source coupled to a first node; a second transistor having a gate coupled to the second input node; a third transistor having a drain coupled to a drain of the first transistor; a fourth transistor having a gate coupled to a gate of the third transistor; a first resistor; a second resistor; a fifth transistor having a gate coupled to the drain of the first transistor; a sixth transistor having a gate coupled to the drain of the second transistor; a seventh transistor having a source coupled to the first node; an eighth transistor having a gate coupled to a gate of the seventh transistor; a third resistor; and a fourth resistor.

Abstract: An image forming system includes a first storage unit that stores identification information and storage information with the identification information mapped to the storage information, the identification information identifying a user, the storage information indicating a storage location where image data corresponding to the identification information is stored, an identifying unit that, in response to the identification information input by the user, identifies the storage location indicated by the storage information stored on the first storage unit with the identification information mapped thereto, a retrieval unit that retrieves, from the storage location identified by the identifying unit, the image data corresponding to the identification information, and an image forming unit that forms an image responsive to the image data retrieved by the retrieval unit.