Patents by Inventor Kazuaki Oishi
Kazuaki Oishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7855601Abstract: A semiconductor device including: a gain control circuit; a first circuit which is controlled a gain to be constant by the gain control circuit; and a bias circuit connected to the first circuit, wherein the first circuit including a first transistor; and a load resistance, an amplification factor or an attenuation factor of the first circuit is proportionate to a product of a transconductance of the first transistor and a resistance value of the load resistance, and a voltage applied to the load resistance is set as an output of the semiconductor device, the bias circuit generates and outputs a differential current of a current that is proportionate to a drain current flowing into the first transistor and a current that is inversely proportionate to the load resistance value, and an output of the bias circuit is connected to an output node of the first circuit.Type: GrantFiled: March 16, 2009Date of Patent: December 21, 2010Assignee: Fujitsu LimitedInventor: Kazuaki Oishi
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Patent number: 7835462Abstract: A comparator compares the voltage of an envelope signal by applying envelope detection to a signal amplitude-modulated by a digital signal encoded by a Manchester code with the terminal voltage of a capacitor constituting a filter for converting the output current of a charge pump into a voltage. The charge pump charges/discharges the capacitor by discharging or charging current, according to the result of the comparison.Type: GrantFiled: August 18, 2006Date of Patent: November 16, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Kazuaki Oishi
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Publication number: 20100283527Abstract: An analog switch comprises a first transistor, a second transistor, the drain and the source thereof being connected between said first input terminal and a second output terminal whereto said second signal is output and the gate thereof being grounded or connected to a supply voltage node, a third transistor, the drain and the source thereof being connected between a second input terminal whereto said second signal is input and said second output terminal and said third transistor being turned on and off by a control signal provided to the gate thereof; and a fourth transistor, the drain and the source thereof being connected between said second input terminal and said first output terminal and the gate thereof being grounded or connected to a supply voltage node.Type: ApplicationFiled: July 20, 2010Publication date: November 11, 2010Applicant: FUJITSU LIMITEDInventors: Kazuaki OISHI, Masahiro KUDO
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Publication number: 20100171549Abstract: This variable gain amplifier is provided with an operational amplifier. The non-inversion input terminal of the operational amplifier is connected to a reference potential. A feedback resistor is connected between the output terminal and inversion input terminal of the operational amplifier. An input resistor is inserted between the inversion input terminal of the operational amplifier and the input terminal of the variable gain amplifier circuit. An adjustment resistor is connected between the inversion input terminal of the operational amplifier and the reference potential. The resistance value of the adjustment resistor is controlled in such a way as to maintain constant against the resistance value change a combined resistance value in its parallel connection with the input resistor when changing the resistance value of the input resistor.Type: ApplicationFiled: January 21, 2010Publication date: July 8, 2010Applicant: FUJITSU LIMITEDInventor: Kazuaki Oishi
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Patent number: 7746168Abstract: A bias circuit of a resistance load differential amplifier comprises a first differential pair and a control unit for controlling a tail current of the first differential pair, and making an output current of the first differential pair being in inverse proportion to a load resistance in the resistance load differential amplifier when applying a constant potential difference to an input of the first differential pair. The control unit further controls a tail current of a second differential pair constituting the resistance load differential amplifier, and makes the tail current of the second differential pair being in direct proportion to the tail current of the first differential pair.Type: GrantFiled: August 17, 2006Date of Patent: June 29, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Kazuaki Oishi
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Patent number: 7679447Abstract: This variable gain amplifier is provided with an operational amplifier. The non-inversion input terminal of the operational amplifier is connected to a reference potential. A feedback resistor is connected between the output terminal and inversion input terminal of the operational amplifier. An input resistor is inserted between the inversion input terminal of the operational amplifier and the input terminal of the variable gain amplifier circuit. An adjustment resistor is connected between the inversion input terminal of the operational amplifier and the reference potential. The resistance value of the adjustment resistor is controlled in such a way as to maintain constant against the resistance value change a combined resistance value in its parallel connection with the input resistor when changing the resistance value of the input resistor.Type: GrantFiled: December 3, 2007Date of Patent: March 16, 2010Assignee: Fujitsu LimitedInventor: Kazuaki Oishi
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Patent number: 7667523Abstract: An orthogonal signal output circuit having an error correction function for correcting an orthogonal error, including: first and second differential circuits; and first to fourth variable resistors, wherein the first variable resistor is connected to a positive output of the first differential circuit and a positive output of the second differential circuit; the second variable resistor is connected to the positive output of the first differential circuit and a negative output of the second differential circuit; the third variable resistor is connected to a negative output of the first differential circuit and the positive output of the second differential circuit; and the fourth variable resistor is connected to the negative output of the first differential circuit and the negative output of the second differential circuit.Type: GrantFiled: March 16, 2009Date of Patent: February 23, 2010Assignee: Fujitsu LimitedInventors: Kazuaki Oishi, Nobuhiko Kobayashi, Masahiro Kudo
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Patent number: 7633346Abstract: A transconductance compensating bias circuit is disclosed that includes a first field-effect transistor (FET) having a first electrode, a second electrode, and a gate connected to the first electrode, wherein a reference current flows through the first and second electrodes; a second FET having a first electrode, a second electrode, and a gate connected to the gate of the first FET, wherein a bias current flows through the first and second electrodes; a resistor connected to the second electrode of the first or second FET; and a comparison part configured to output a signal corresponding to the result of comparison of the first potential of the first electrode of the first FET and the second potential of the first electrode of the second FET. The reference current and the bias current are controlled by the output signal of the comparison part so as to equalize the first and second potentials.Type: GrantFiled: July 31, 2008Date of Patent: December 15, 2009Assignee: Fujitsu LimitedInventor: Kazuaki Oishi
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Publication number: 20090302947Abstract: A semiconductor device including: a gain control circuit; a first circuit which is controlled a gain to be constant by the gain control circuit; and a bias circuit connected to the first circuit, wherein the first circuit including a first transistor; and a load resistance, an amplification factor or an attenuation factor of the first circuit is proportionate to a product of a transconductance of the first transistor and a resistance value of the load resistance, and a voltage applied to the load resistance is set as an output of the semiconductor device, the bias circuit generates and outputs a differential current of a current that is proportionate to a drain current flowing into the first transistor and a current that is inversely proportionate to the load resistance value, and an output of the bias circuit is connected to an output node of the first circuit.Type: ApplicationFiled: March 16, 2009Publication date: December 10, 2009Applicant: FUJITSU LIMITEDInventor: Kazuaki Oishi
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Publication number: 20090302925Abstract: An orthogonal signal output circuit having an error correction function for correcting an orthogonal error, including: first and second differential circuits; and first to fourth variable resistors, wherein the first variable resistor is connected to a positive output of the first differential circuit and a positive output of the second differential circuit; the second variable resistor is connected to the positive output of the first differential circuit and a negative output of the second differential circuit; the third variable resistor is connected to a negative output of the first differential circuit and the positive output of the second differential circuit; and the fourth variable resistor is connected to the negative output of the first differential circuit and the negative output of the second differential circuit.Type: ApplicationFiled: March 16, 2009Publication date: December 10, 2009Applicant: FUJITSU LIMITEDInventors: Kazuaki Oishi, Nobuhiko Kobayashi, Masahiro Kudo
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Patent number: 7629846Abstract: Based on a result of comparing an output common mode direct-current voltage of a pair of source follower transistors when a direct-current voltage is applied to each gate of the pair of source follower transistors with a predetermined reference voltage, the direct-current voltage is controlled such that the output common mode direct-current voltage can match the reference voltage.Type: GrantFiled: November 15, 2007Date of Patent: December 8, 2009Assignee: Fujitsu LimitedInventor: Kazuaki Oishi
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Patent number: 7629853Abstract: An amplifying apparatus including an amplifier having a first FET, a second FET having a source connected to a drain of the first FET, a load resistance connected to a drain of the second FET, a first bias circuit configured to supply a first bias voltage to a gate of the first FET, and a second bias circuit configured to supply a second bias voltage to a gate of the second FET. The second bias circuit includes a second comparison circuit configured to send a control signal to the gate of the second FET so that a bias voltage of a connection node between the first and second FETs changes in conjunction with an output voltage of the first bias circuit.Type: GrantFiled: August 26, 2008Date of Patent: December 8, 2009Assignee: Fujitsu LimitedInventor: Kazuaki Oishi
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Publication number: 20090291661Abstract: A noise cancellation circuit, which reduces noise in an output signal of an amplifier having an input resistance, a feedback resistance, and an operational amplifier, has: a first mixer circuit, which input an input signal across a first input terminal and a second input terminal of the operational amplifier, and performs frequency conversion of the input signal according to a first frequency signal; a noise cancellation amplifier, which amplifies an output signal of the first mixer circuit; a second mixer circuit, which performs frequency conversion of an output signal of the noise cancellation amplifier according to the first frequency signal; and a signal supply circuit, which supplies an output signal of the second mixer circuit to the first input terminal of the operational amplifier via an output resistance.Type: ApplicationFiled: May 26, 2009Publication date: November 26, 2009Applicant: FUJITSU LIMITEDInventors: Kazuaki OISHI, Shingo Sakamoto
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Publication number: 20090108941Abstract: A transconductance compensating bias circuit is disclosed that includes a first field-effect transistor (FET) having a first electrode, a second electrode, and a gate connected to the first electrode, wherein a reference current flows through the first and second electrodes; a second FET having a first electrode, a second electrode, and a gate connected to the gate of the first FET, wherein a bias current flows through the first and second electrodes; a resistor connected to the second electrode of the first or second FET; and a comparison part configured to output a signal corresponding to the result of comparison of the first potential of the first electrode of the first FET and the second potential of the first electrode of the second FET. The reference current and the bias current are controlled by the output signal of the comparison part so as to equalize the first and second potentials.Type: ApplicationFiled: July 31, 2008Publication date: April 30, 2009Applicant: FUJITSU LIMITEDInventor: Kazuaki Oishi
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Publication number: 20090108939Abstract: An amplifying apparatus including an amplifier having a first FET, a second FET having a source connected to a drain of the first FET, a load resistance connected to a drain of the second FET, a first bias circuit configured to supply a first bias voltage to a gate of the first FET, and a second bias circuit configured to supply a second bias voltage to a gate of the second FET. The second bias circuit includes a second comparison circuit configured to send a control signal to the gate of the second FET so that a bias voltage of a connection node between the first and second FETs changes in conjunction with an output voltage of the first bias circuit.Type: ApplicationFiled: August 26, 2008Publication date: April 30, 2009Applicant: FUJITSU LIMITEDInventor: Kazuaki Oishi
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Publication number: 20080218244Abstract: An analog switch comprises a first transistor, a second transistor, the drain and the source thereof being connected between said first input terminal and a second output terminal whereto said second signal is output and the gate thereof being grounded or connected to a supply voltage node, a third transistor, the drain and the source thereof being connected between a second input terminal whereto said second signal is input and said second output terminal and said third transistor being turned on and off by a control signal provided to the gate thereof; and a fourth transistor, the drain and the source thereof being connected between said second input terminal and said first output terminal and the gate thereof being grounded or connected to a supply voltage node.Type: ApplicationFiled: March 4, 2008Publication date: September 11, 2008Inventors: Kazuaki Oishi, Masahiro Kudo
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Publication number: 20080211597Abstract: A filter circuit including first and second real filters of a zero-IF scheme. The first and second real filters receive an I component and a Q component separated from a reception signal, respectively; and a switch section for producing a complex filter by switchably connecting the first and second real filters through interconnection elements. The switch section further receiving a switching signal for connecting the first and second real filters, thereby switching from the zero-IF scheme to a low-IF scheme.Type: ApplicationFiled: February 20, 2008Publication date: September 4, 2008Applicant: FUJITSU LIMITEDInventors: Daisuke Yamazaki, Kazuhiko Kobayashi, Kazuaki Oishi
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Publication number: 20080197926Abstract: Based on a result of comparing an output common mode direct-current voltage of a pair of source follower transistors when a direct-current voltage is applied to each gate of the pair of source follower transistors with a predetermined reference voltage, the direct-current voltage is controlled such that the output common mode direct-current voltage can match the reference voltage.Type: ApplicationFiled: November 15, 2007Publication date: August 21, 2008Applicant: FUJITSU LIMITEDInventor: Kazuaki Oishi
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Publication number: 20080197924Abstract: This variable gain amplifier is provided with an operational amplifier. The non-inversion input terminal of the operational amplifier is connected to a reference potential. A feedback resistor is connected between the output terminal and inversion input terminal of the operational amplifier. An input resistor is inserted between the inversion input terminal of the operational amplifier and the input terminal of the variable gain amplifier circuit. An adjustment resistor is connected between the inversion input terminal of the operational amplifier and the reference potential. The resistance value of the adjustment resistor is controlled in such a way as to maintain constant against the resistance value change a combined resistance value in its parallel connection with the input resistor when changing the resistance value of the input resistor.Type: ApplicationFiled: December 3, 2007Publication date: August 21, 2008Inventor: Kazuaki Oishi
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Patent number: 7315199Abstract: This is a filter circuit for keeping a Q value constant and stabilizing the gain ripple and group delay ripple of a filter by keeping the unity gain frequency of an operational amplifier (op-amp). The filter circuit using an op-amp for keeping the cut-off frequency constant by making a resistance or a capacitance value variable comprises a unity gain angular frequency stabilizing circuit provided with a circuit obtained by copying the input differential stage of the operational amplifier, for connecting a current generating source for generating current under the control of keeping the cut-off frequency constant, for adjusting the output of the copy of the input differential stage and feeding back/inputting the adjusted output to the gate of a transistor, and a circuit for inputting the output of the unity gain angular frequency stabilizing circuit to the gate of the transistor for generating the bias current of the input differential stage of each op-amp.Type: GrantFiled: July 5, 2005Date of Patent: January 1, 2008Assignee: Fujitsu LimitedInventor: Kazuaki Oishi