Patents by Inventor Kazuaki Tamura

Kazuaki Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7793192
    Abstract: A semiconductor memory device in which data is not written in a transfer destination under a state including an error when an error occurs at the time of reading data at the transfer destination. The semiconductor memory device (1) comprising a nonvolatile memory (2) having a data writing unit smaller than a physical block is provided with an error detecting/correcting circuit (23) in the non-volatile memory (2). When data stored in a specified block of the non-volatile memory (2) is transferred to a different physical block and written, the error detecting/correcting circuit (23) performs error detection and correction of data.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: September 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazuaki Tamura, Tomoaki Izumi, Tetsushi Kasahara, Masahiro Nakanishi, Kiminori Matsuno, Manabu Inoue
  • Publication number: 20100191055
    Abstract: The present invention provides a capsule type medical apparatus that can receive, in a subject, an external signal transmitted from an outside of the subject and transmitted via a conductor existing in the subject, including: a cover member that is formed of a dielectric and covers components of the capsule type medical apparatus; a plurality of electrodes that are formed of conductors, are provided in tight contact with an inner wall side of the cover member, and receive the external signal; an inductor circuit that is connected in series to each of the plurality of electrodes, and has an inductance value set to configure a resonant circuit having a frequency substantially equal to a carrier frequency of the external signal as a resonant frequency; and a signal receiving circuit to which the external signal received by the plurality of electrodes and a potential difference of the external signal are inputted.
    Type: Application
    Filed: March 31, 2010
    Publication date: July 29, 2010
    Applicant: OLYMPUS CORPORATION
    Inventors: Tetsuo MINAI, Kazuaki TAMURA, Jin OHARA
  • Publication number: 20100137708
    Abstract: From among plural receiver electrodes for receiving a transmission signal transmitted from transmitter electrodes of an intra-subject introduction device, receiver electrodes for receiving an image reception signal are selected by a receiver electrode selection circuit. Further, receiver electrodes for receiving a signal for position detection are selected by a receiver electrode selection circuit, from among the other ones of the plural receiver electrodes than the receiver electrodes selected by the receiver electrode selection circuit.
    Type: Application
    Filed: February 2, 2010
    Publication date: June 3, 2010
    Applicants: OLYMPUS CORPORATION, OLYMPUS MEDICAL SYSTEMS CORP.
    Inventors: Kazuaki TAMURA, Takeshi MORI, Tetsuo MINAI, Akio UCHIYAMA
  • Patent number: 7702846
    Abstract: A nonvolatile storage device is provided with a nonvolatile main storage memory whose erase size is larger than a cluster size, and a buffer, i.e. a nonvolatile auxiliary storage memory. At the time of writing data in the memory, the data is temporarily stored in the buffer, then, a plurality of data in the buffer are collectively taken out to be stored in the main storage memory. Data in an original block is saved in a write block in the main storage memory. Thus, the data can be written in the main storage memory at a high speed.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: April 20, 2010
    Assignee: Panasonic Corporation
    Inventors: Masahiro Nakanishi, Tomoaki Izumi, Tetsushi Kasahara, Kazuaki Tamura, Kiminori Matsuno, Yutaka Nakamura, Masayuki Toyama, Yasushi Goho, Syunichi Iwanari, Yoshihisa Kato, Manabu Inoue
  • Patent number: 7654466
    Abstract: A host information memory is provided in a semiconductor memory card and a data write start address and a data size supplied by an access unit are stored. A free physical area generation section determines whether or not to perform erasing of an invalid block of a nonvolatile memory when writing of data based on the data write start address and data size, and determines the number of blocks to be erased. When erasing, writing of data and erasing of invalid blocks are simultaneously performed with respect to different memory chips. Erase process of data, herewith, can be optimized and high speed access from the access unit to a semiconductor memory card can be realized.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: February 2, 2010
    Assignee: Panasonic Corporation
    Inventors: Takuji Maeda, Shinji Inoue, Yoshiho Gotoh, Jun Ohara, Masahiro Nakanishi, Shoichi Tsujita, Tomoaki Izumi, Tetsushi Kasahara, Kazuaki Tamura, Kiminori Matsuno, Koichi Horiuchi, Manabu Inoue
  • Patent number: 7633817
    Abstract: A controller 102 and four flash memories F0 to F3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address specified by a host apparatus is divided into a predetermined size, and a write operation is performed in a format that repeatedly circulates through F0, F1, F2, F3 in this order. In a two-memory configuration, the write operation is performed in a format that repeatedly circulates through F00, F10, F01, F11. Thus, a controller processing is made common regardless of the number of flash memories connected to the controller.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: December 15, 2009
    Assignee: Panasonic Corporation
    Inventors: Masahiro Nakanishi, Tomoaki Izumi, Tetsushi Kasahara, Kazuaki Tamura, Kiminori Matsuno
  • Patent number: 7624298
    Abstract: A memory card (1) includes a host interface (2) that transmits and receives a command and data to and from the data processor (50), a nonvolatile memory (7) that stores data, a controller (3) that controls the operation of the memory card, and a storage section (32) that stores specified management information. The management information includes retry setting information which specifies whether a retry function is executed or not when an error occurs during an operation of writing data to the nonvolatile memory. The controller (3) refers to the retry setting information in the data writing operation, and controls the data writing operation so as to disable the retry function in the event of an error in the data writing operation, when the retry setting information indicates disabling of the retry function or to enable the retry function in the event of an error in the data writing operation, when the retry setting information indicates enabling of the retry function.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: November 24, 2009
    Assignee: Panasonic Corporation
    Inventors: Tetsushi Kasahara, Tomoaki Izumi, Masahiro Nakanishi, Kazuaki Tamura, Kiminori Matsuno
  • Patent number: 7610435
    Abstract: A writing completion flag table that stores a writing completion flag corresponding to a predetermined storage, such as a cluster or a physical block, is stored in a non-volatile control memory. When completion of data writing into a predetermined storage is detected, a write completion flag is written in the corresponding address of the storage on the write completion flag table. Thus, it is possible to recognize that data has been written normally. Even when the flag indicating completion of writing into a page of the writing unit of the main storage memory cannot be written, it is possible to improve the writing reliability.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: October 27, 2009
    Assignee: Panasonic Corporation
    Inventors: Masahiro Nakanishi, Tomoaki Izumi, Tetsushi Kasahara, Kazuaki Tamura, Kiminori Matsuno, Manabu Inoue
  • Publication number: 20090210612
    Abstract: In rewriting processing of logical sectors, data of the transferred logical sectors are temporarily stored in a memory buffer. When the buffer memory has been full filled with data, the data is written into a flash memory. In rewriting processing for the flash memory including a writing unit (page) having a capacity larger than a minimum writing unit (sector) from outside, the number of executions of the evacuation processing can be reduced and the fast data rewriting can be performed. Thus, it is possible to rationalize the evacuation processing for old data caused in the rewriting in units of sectors and to improve the data rewriting speed.
    Type: Application
    Filed: March 12, 2007
    Publication date: August 20, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masahiro Nakanishi, Masayuki Toyama, Yutaka Nakamura, Yasushi Gohou, Masanori Matsuura, Manabu Inoue, Tomoaki Izumi, Tetsushi Kasahara, Kazuaki Tamura, Kiminori Matsuno, Shunichi Iwanari, Shinichi Tokumitsu
  • Publication number: 20090191449
    Abstract: An alkaline storage battery in which an actual reaction area is not reduced after increasing a reaction area is provided. A hydrogen storage alloy negative electrode 11 of an alkaline storage battery 10 of the present invention is formed in a strip form including a long axis and a short axis, in which the ratio (A/B) of a length A (cm) of the long axis to a length B (cm) of the short axis is 20 or more and 30 or less (20?A/B?30), and the ratio (X/Y) of an electrolyte volume X (g) retained in the hydrogen storage alloy negative electrode 11 to an electrolyte volume Y (g) retained in a separator 13 is 0.8 or more and 1.1 or less (0.8?X/Y?1.1). With this arrangement, an alkaline storage battery with high output characteristics and long-term durability performance is obtained.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 30, 2009
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shuhei YOSHIDA, Yoshinobu KATAYAMA, Kazuaki TAMURA, Teruhito NAGAE
  • Publication number: 20090169995
    Abstract: A hydrogen storage alloy of the present invention includes component A including a rare earth element represented by Ln and magnesium and component B including elements containing at least nickel and aluminum, wherein a primary alloy phase of a hydrogen storage alloy represents an A5B19 type structure; a general formula is represented as Ln1-xMgxNiy-a-bAlaMb (wherein M represents at least one element selected from Co, Mn, and Zn; and 0.1?x?0.2, 3.6?y?3.9, 0.1?a?0.2, and 0?b?0.1); a rare earth element Ln includes maximally two elements containing at least La; and absorption hydrogen equilibrium pressure (Pa) is 0.03-0.17 MPa when the hydrogen amount absorbed in the hydrogen storage alloy (H/M (atomic ratio)) at 40° C. is 0.5.
    Type: Application
    Filed: December 22, 2008
    Publication date: July 2, 2009
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shuhei YOSHIDA, Kazuaki TAMURA, Yoshinobu KATAYAMA, Teruhito NAGAE
  • Publication number: 20090061316
    Abstract: A hydrogen storage alloy used in a hydrogen storage alloy electrode 11 has a crystalline structure having a mixed phase made up of at least an A2B7 type structure and an A5B19 type structure, and a surface layer of hydrogen storage alloy particles is so formed as to have a nickel content ratio greater than that of a bulk. The ratio (X/Y) of the nickel content ratio X (% by mass) of the surface layer to the nickel content ratio Y (% by mass) of the bulk is greater than 1.0 but no more than 1.2 (1.0<X/Y?1.2). The gradient between the content ratio of the nickel in the surface layer of the hydrogen storage alloy particles and the content ratio of the nickel in the bulk is alleviated and a hydrogen storage alloy electrode with high output characteristics is obtained.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 5, 2009
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shuhei YOSHIDA, Kazuaki TAMURA, Yoshinobu KATAYAMA, Teruhito NAGAE, Masao TAKEE
  • Publication number: 20090055618
    Abstract: For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.
    Type: Application
    Filed: July 21, 2006
    Publication date: February 26, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masahiro Nakanishi, Tetsushi Kasahara, Tomoaki Izumi, Kiminori Matsuno, Daisuke Kunimune, Kazuaki Tamura, Yoshiyuki Konishi
  • Publication number: 20090055576
    Abstract: A nonvolatile storage device is provided with a nonvolatile main storage memory (114) whose erase size is larger than a cluster size, and a buffer (106), i.e. a nonvolatile auxiliary storage memory. At the time of writing data in the memory, the data is temporarily stored in the buffer (106), then, a plurality of data in the buffer (106) are collectively taken out to be stored in the main storage memory (114). Data in an original block is saved in a write block in the main storage memory. Thus, the data can be written in the main storage memory (114) at a high speed.
    Type: Application
    Filed: March 9, 2006
    Publication date: February 26, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masahiro Nakanishi, Tomoaki Izumi, Tetsushi Kasahara, Kazuaki Tamura, Kiminori Matsuno, Yutaka Nakamura, Masayuki Toyama, Yasushi Goho, Syunichi Iwanari, Yoshihisa Kato, Manabu Inoue
  • Publication number: 20090019194
    Abstract: When a control unit (160) in a storage device (100) detects that a write end command or a data amount to be written has been transmitted from a host device (110), the control unit (160) saves control information required for writing data in a control information save memory (142). The control unit (160) also saves data which has not been written in storage medium into a buffer save memory (152) from a data buffer (151) and releases the busy state for the host device (110). The control unit (160) writes the saved data into a storage medium (120). Even if the power is turned OFF before completion of write, write can be performed into the storage medium (120) by using the saved data when the power is turned ON next time.
    Type: Application
    Filed: March 24, 2006
    Publication date: January 15, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masayuki Toyama, Masahiro Nakanishi, Tomoaki Izumi, Tetsushi Kasahara, Kazuaki Tamura, Kiminori Matsuno, Manabu Inoue
  • Patent number: 7475185
    Abstract: When a file system control part 155A writes file data into a main memory 142, a file can be easily written continuously and the number of file copy can be decreased at updating a directory entry by writing the file data and a directory entry into different allocation units. In this manner, when using a nonvolatile memory in which physical block size as an erase unit is larger than cluster size, the write performance can be enhanced.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: January 6, 2009
    Assignee: Panasonic Corporation
    Inventors: Masahiro Nakanishi, Tomoaki Izumi, Tetsushi Kasahara, Kazuaki Tamura, Kiminori Matsuno, Shouichi Tsujita, Takuji Maeda, Shinji Inoue, Manabu Inoue, Masayuki Toyama, Keisuke Sakai
  • Publication number: 20080307152
    Abstract: In a storage having a nonvolatile RAM of destructive read type, the number of restorations attributed to data read from the nonvolatile RAM is decreased, and the overall life of the storage is prolonged. In a storage having a nonvolatile RAM of destructive read type and a volatile RAM and holding the same data in the nonvolatile and volatile RAMs, data is read out of the volatile RAM in reading and data is written in both volatile and nonvolatile RAMs in writing.
    Type: Application
    Filed: March 1, 2006
    Publication date: December 11, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masahiro Nakanishi, Tomoaki Izumi, Tetsushi Kasahara, Kazuaki Tamura, Kiminori Matsuno, Manabu Inoue, Masayuki Toyama, Kunihiro Maki
  • Publication number: 20080299458
    Abstract: To provide a hydrogen storage alloy for an alkaline battery capable of having high performance of power characteristics much more beyond the related-art range, and a production method thereof, as well as an alkaline battery by investigating the constituent ratios of the A2B7-type structure and the A5B19-type structure. The hydrogen storage alloy for an alkaline battery of the present invention includes: an element R selected from the Group IV and the rare earth elements including Y and excluding La; and an element M consisting of at least one of Co, Mn, and Zn. The hydrogen storage alloy is represented by general formula: La?R1-?-?Mg?Ni?-?-?Al?M? (wherein ?, ?, ?, ?, ? satisfy numerical formulae: 0???0.5, 0.1???0.2, 3.7???3.9, 0.1???0.3, 0???0.2); and the constituent ratio of the A5B19-type structure is 40% or more in the crystal structure thereof.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 4, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shuhei YOSHIDA, Kazuaki TAMURA, Yoshinobu KATAYAMA, Teruhito NAGAE, Masao TAKEE
  • Publication number: 20080288710
    Abstract: A card information storage part (119) is provided in a semiconductor memory device (110) to store information of the characteristics of the semiconductor memory device (110). There is also provided a file system interface control part (120) for performing, based on the stored characteristic information, a file access suitable for the characteristics of the semiconductor memory device (110). This allows an access device (100) to perform an optimum file access via the file system interface control part (120) without awareness of the characteristics of the semiconductor memory device (110).
    Type: Application
    Filed: January 24, 2005
    Publication date: November 20, 2008
    Inventors: Takuji Maeda, Shinji Inoue, Shoichi Tsujita, Yoshiho Gotoh, Jun Ohara, Kiminori Matsuno, Kazuaki Tamura
  • Publication number: 20080250188
    Abstract: A physical area management table (105) and a pointer table (106) are stored in a nonvolatile auxiliary storage memory (107). When a logical-physical conversion table (108) is updated (restored) in a main storage memory (140), the restored area is determined in a re-arrangement way by the pointer table to avoid rewrite concentration on the main storage memory (140). Immediately after data is written in the main storage memory (140), the state of the physical block on the physical area management table (105) is updated. Consequently, even if power interruption occurs, it is possible to reliably judge if the data is valid or not.
    Type: Application
    Filed: November 17, 2005
    Publication date: October 9, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Nakanishi, Tomoaki Izumi, Tetsushi Kasahara, Kazuaki Tamura, Kiminori Matsuno, Manabu Inoue, Masayuki Toyama, Kunihiro Maki