Abstract: A sales system for selling semiconductor devices by way of a communication network comprises a device information processing unit for obtaining function-related information on semiconductor devices to be possibly purchased from the client terminals by way of the communication network. The device information processing unit is arranged in a processor for presenting function-related information and price-related information on partially good semiconductor devices having one or more than one unusable functions and the functions specified in the function-related information obtained by the device information processing unit, prompting the client terminals to provide purchase/non-purchase information, obtaining purchase/non-purchase information on the partially good products from the client terminals and determining the possibility of successful transactions on the basis of the purchase/non-purchase information provided from client terminals.

Abstract: A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The second latch circuit group sequentially outputs the remaining n/2 bit read data in response to the sequentially shifted read control signal.

Abstract: A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device.

Abstract: A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device.

Abstract: An output buffer generates "1" or "0" data based on control signals VA and VB transferred from memory cells through a DQ gate in a DRAM. The output buffer has first and second discharge circuits, and a first output transistor (PMOS Transistor). The second discharge circuit stops discharging the gate of the first output transistor after the voltage on the gate drops below the threshold voltage of the first output transistor and the first output transistor turns ON. After this time, only the first discharge circuit discharges the gate of the first output transistor. Further, the output buffer has first and second precharge circuits, and a second output transistor (NMOS transistor). The second precharge circuit stops charging the gate of the second output transistor after the voltage on the gate increases above the threshold voltage of the second output transistor and the second output transistor turns ON.