Abstract: A semiconductor device comprises a first transistor connected between a bit line and a sense node, and a second transistor amplifying a signal of the sense node. A first potential applied to a gate of the first transistor, a second potential supplied to the sense node, and a third potential supplied to the bit line are controlled so that the first potential applied to a gate of the first transistor is between the second and third potentials, the second potential is set larger than the third potential, and a predetermined potential obtained by subtracting a threshold voltage of the first transistor from the first potential is smaller than the third potential and higher than a low potential supplied to the second transistor. A potential of the bit line transitions from the third potential toward the low potential in accordance with data of a current change memory cell.

Abstract: In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to t

Abstract: A semiconductor device has a hierarchical bit line structure and comprises first and second local bit lines transmitting first and second signals of first and second memory cells corresponding to a selected word line, and first and second global bit lines electrically connected to the first and second local bit lines through first and second switches, first and second sense amplifiers connected to the first and second global bit lines, and a control circuit. During a first period after the first and second memory cells are simultaneously accessed, the control circuit controls the first switch to conduction state so that the first sense amplifier amplifies the first signal and controls the second switch to non conduction state. During a second period after sensing of the first sense amplifier finishes, the control circuit controls the second switch to conduction state so that the second sense amplifier amplifies the second signal.

Abstract: A semiconductor device includes a bit line, a memory cell coupled to the bit line, the memory cell being configured such that a current flowing there the memory cell is varied in accordance with information stored M the memory cell, a first transistor coupled at a control electrode thereof to the bit line, a second transistor coupled to the bit line and supplied at a control electrode thereof with a first control signal, a global bit line, and a third transistor coupled in series with the first sistor between a node and the global bit line, the third transistor supplied at a control electrode thereof with a second control signal.

Abstract: A semiconductor device includes a semiconductor substrate, a non-volatile semiconductor memory element formed over the semiconductor substrate, including a variable resistance element including a laminate comprising a first electrode, a variable resistance layer, and a second electrode, and a volatile semiconductor memory element formed over the semiconductor substrate, including a capacitance element including a laminate comprising a third electrode, a dielectric layer including a same material as the variable resistance layer, and a fourth electrode.

Abstract: A semiconductor device comprises a first sense amplifier, first to third transmission lines, and first to third switches. The first and second transmission lines are connected to the first sense amplifier. The first and third switches control connections of the first to third transmission lines, and the second switch controls a connection between a fixed potential and third transmission line. When the second transmission line is not accessed, the first and third switches are brought into a non-conductive state and the second switch is brought into a conductive state, and the fixed potential is supplied to the third transmission line, thereby suppressing influence of the coupling noise between the transmission lines.

Abstract: A semiconductor device comprises transmission lines, inverting circuits, first, second and third switches, global sense amplifiers, and a control circuit. The first switch switches between the transmission line and the input of the inverting circuit, the second switch switches between the transmission line and the output of the transmission line, and the third switch switches between the adjacent transmission lines. The control circuit turns off the first and second switches so that the transmission lines are brought into a floating state in a state where signals of the transmission lines are held in the inverting circuits by the global sense amplifiers. After charge sharing of the transmission lines occurs by turning on the third switches within a predetermined period, the control circuit turns off the second switches so that the transmission lines are inverted and driven via the inverting circuits and the second switches.

Abstract: A single-ended sense amplifier circuit comprises first and second MOS transistors and first and second voltage setting circuits. The first MOS transistor supplies a predetermined voltage to the bit line and switches connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor having a gate connected to the sense node amplifies a signal transmitted from the bit line via the first MOS transistor. The first voltage setting circuit sets the bit line to a first voltage, and the second voltage setting circuit sets the sense node to a second voltage. In the sense amplifier circuit, after setting the bit line and the sense node to respective voltages, the bit line is driven in a charge distributing mode via the first MOS transistor so that a signal voltage at the sense node is amplified by the second MOS transistor.

Abstract: A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor has a gate connected to the sense node and amplifies a signal transmitted from the bit line via the first MOS transistor. The predetermined voltage is supplied to the bit line before read operation and is set to a value such that a required voltage difference at the sense node between high and low level data of the memory cell can be obtained near a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell.

Abstract: A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof.

Abstract: A sense amplifier in a semiconductor storage device includes a memory cell for storing information on the basis of the size of the resistance value between a signal input/output terminal and a power supply terminal, the semiconductor storage device having a structure in which the bit line capacitance during signal reading from the memory cell is reduced, wherein the amplifier amplifies a signal outputted from an input/output terminal through the use of a single MOS transistor that has a single-ended structure.

Abstract: A semiconductor device comprises a first circuit outputting a signal to a first signal line, a first FET applied with a driving signal and having a gate electrode connected to a first node, a second FET controlling an electrical connection between the first signal line and the first node, a third FET amplifying a signal of the first node, a second circuit precharging the first signal line, and a voltage control circuit. A gate capacitance of the first FET is controlled in response to a voltage difference between the first node and the driving signal. The voltage control circuit shifts a potential of the driving signal when the second FET is non-conductive after the signal of the first-circuit is transmitted to the first node, and performs an offset control for the driving signal so as to compensate a variation of a threshold voltage of the first FET.

Abstract: A semiconductor device comprises a first memory cell array, a register storing information of whether or not one of the word lines in an active state exists in a unit area and storing address information, and a control circuit controlling a refresh operation for a refresh word line based on the information in the register when receiving a refresh request. When the one of the word lines in an active state does not exist, memory cells connected to the refresh word line are refreshed. When the one of the word lines in an active state exists, the one of the word lines in an active state is set into an inactive state temporarily and the memory cells connected to the refresh word line are refreshed after precharging bit lines of the memory cells.

Abstract: A method of manufacturing a semiconductor memory device of the present invention consists of a step of forming a selection transistor and a separate selection transistor and a step of forming a variable resistance element and a capacitance element, characterized by forming the variable resistance element by sequentially laminating a first electrode that is connected to the selection transistor, a variable resistance layer, and a second electrode; forming the capacitance element by sequentially laminating a third electrode that is connected to the separate selection transistor, a dielectric layer, and a fourth electrode; forming the dielectric layer and the variable resistance layer with a mutually identical material; forming either one of the first electrode or the second electrode with the same material as the third electrode and the fourth electrode; and forming the other one of the first electrode or the second electrode with a different material than the third electrode and the fourth electrode.

Abstract: A data processing system includes a first semiconductor device that has a plurality of blocks each including plural data, and a second semiconductor device that has a first control circuit controlling the first semiconductor device, and the first control circuit issues a plurality of commands to communicate with the first semiconductor device in units of access units including a plurality of first definitions that define a plurality of burst lengths indicating numbers of different data, respectively, and a plurality of second definitions that define correspondences between certain elements of data among the plural data included in the blocks, respectively, and arrangement orders in the numbers of different data that constitute the burst lengths, respectively, and communicates with the first semiconductor device through the plural data in the numbers of different data according to the first and second definitions.

Abstract: A semiconductor device includes a sense amplifier, transistors selectively establishing electrical connection between the sense amplifier and a data bus, depending on address; a write amplifier connected to the data bus, an external terminal outputting data from a memory cell to outside via the sense amplifier, the transistors, and the data bus in a first operation mode and supplying data from outside to the sense amplifier via the write amplifier, the data bus, and the transistors in a second operation mode, and a control circuit supplying an electric potential to gate electrodes of first transistors that establish the electrical connection depending on the address, wherein in a first operation mode, the control circuit supplies a first electric potential to the gate electrodes of the first transistors, so that the first transistors exhibit a first impedance value and in the second operation mode, the control circuit supplies a second electric potential to gate electrodes of the first transistors, so that th

Abstract: The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal.

Abstract: A device includes a first region including a plurality of first memory elements and a plurality of first vertical transistors, the first vertical transistors comprising a plurality of first selective transistors and a first switching transistor, each of the first selective transistors including an upper electrode coupled to a corresponding one of the first memory elements and a lower electrode, the first switching transistor including an upper electrode and a lower electrode coupled in common to the lower electrodes of the first selective transistors through a first signal line, a second region arranged to make a first line with the first region in a first direction and including a plurality of second memory elements and a plurality of second vertical transistors, the second vertical transistors comprising a plurality of second selective transistors and a second switching transistor, and a third region sandwiched between the first and the second regions.

Abstract: A multi-port memory, comprising: m (m?2) input/output ports independent of one another; n (n?2) memory banks independent of one another; and a route switching circuit capable of optionally setting signal routes of a command, an address, and input/output data between the m input/output ports and the n memory banks, wherein the route switching circuit allocates p (1?p?m) input/output ports optionally selected from the m input/output ports to a memory bank optionally selected from the n memory banks.

Abstract: A device includes a memory cell array having a plurality of memory cells; sense amplifiers, which are arranged adjacent to the memory cell array, for amplifying signals that have been read out of corresponding ones of the memory cells; readout signal lines; a plurality of connection circuits for selectively connecting the sense amplifiers and the readout signal lines; a plurality of main amplifiers for amplifying and outputting signals that have been read out of the sense amplifiers via the readout signal lines by the connection circuits selected by selection signals; an enable signal line connected to the main amplifiers; and an enable signal generating circuit for outputting a main amplifier enable signal to the enable signal line. The enable signal generating circuit is placed in close proximity to the connection circuits.