Abstract: Inductive structures having low parasitic capacitances for direct integration in semiconductor integrated circuits. In one embodiment, a generally planar spiral winding is disposed on the surface of a substrate. An electrical connection to the internal end of the spiral is made through electrically conducting vias passing through the substrate. The spiral may be spaced from a substrate surface by a plurality of spaced apart electrically conductive posts having a staggered arrangement between adjacent windings of the spiral. A transformer includes two windings disposed on top of each other on a semiconductor substrate and separated by an electrically insulating film. The windings have a common central opening in which a magnetic material is disposed to improve the inductive coupling between the windings.

Abstract: A loaded line phase shifter using striplines diposed on a semiconductor substrate includes a main stripline having an electrical length of one-half wavelength, loaded striplines connected to respective ends of the main stripline, a field effect transistor having its source electrode and its drain electrode connected to the respective load lines, a bias circuit connected to the gate electrode of the field effect transistor for controlling the bias voltage applied to the gate electrode, and a resonant stripline connected between the source electrode and the drain electrode.

Abstract: A method of producing MMIC's and the MMIC thus produced having a reproducible quiescent operating point from lot to lot under the same bias conditions. The source to drain saturation current of the amplifier MESFET in the MMIC can vary from lot to lot if the depth of the gate recess varies from lot to lot. As a result, the quiescent operating point of the amplifier under the same bias conditions can vary from lot to lot. A compensated gate bias source, preferably in the form of an extra MESFET on the MMIC, is fabricated at the same time as the amplifier MESFET and thus has a gate recess having a depth which precisely matches that of the amplifier MESFET. The extra MESFET is connected as a compensated gate bias source and has a resistance which is a function of the depth of the gate recess and thus compensates the quiescent operating point of the amplifier MESFET.

Abstract: A method of producing MMIC's and the MMIC thus produced having a reproducible quiescent operating point from lot to lot under the same bias conditions. The source to drain saturation current of the amplifier MESFET in the MMIC can vary from lot to lot if the depth of the gate recess varies from lot to lot. As a result, the quiescent operating point of the amplifier under the same bias conditions can vary from lot to lot. A compensated gate bias source, preferably in the form of an extra MESFET on the MMIC, is fabricated at the same time as the amplifier MESFET and thus has a gate recess having a depth which precisely matches that of the amplifier MESFET. The extra MESFET is connected as a compensated gate bias source and has a resistance which is a function of the depth of the gate recess and thus compensates the quiescent operating point of the amplifier MESFET.