Patents by Inventor Kazuhiro Asada
Kazuhiro Asada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11516953Abstract: A control system of a tape feeder that includes a reel on which is wound component supply tape, and a tape feeding device configured to draw out the component supply tape from the reel to a component pickup position, the control system including a sensor configured to detect information relating to a remaining amount of the tape on the reel; and a motor control section configured to change an operation parameter of a motor that is a drive source of the tape feeding device based on the tape remaining amount information detected by the sensor. Specifically, the motor control section changes the operation parameter of the motor so as to reduce the motor torque as the tape remaining amount on the reel decreases, based on the tape remaining amount information detected by the sensor.Type: GrantFiled: August 25, 2017Date of Patent: November 29, 2022Assignee: FUJI CORPORATIONInventors: Toshiaki Kondo, Kazuhiro Asada
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Patent number: 10795406Abstract: In the case where multiple individual work devices respectively executing a sequence of multiple tasks are controlled in an integrated manner by an integrated control device, log analysis among the multiple individual work devices is difficult. One of four individual work devices transmits time inquiry signal to main integrated control device via serial communication cable. Main integrated control device returns the time at time at which time inquiry signal was received to the one of four individual work devices to which time inquiry signal was transmitted. One of four individual work devices receives a reply from main integrated control device at time, adds the communication time to the time at time, and calculates the time at time. One of four individual work devices starts the calculation of the in-device time from calculated time as a starting point. One of four individual work devices logs based on in-device time.Type: GrantFiled: July 28, 2016Date of Patent: October 6, 2020Assignee: FUJI CORPORATIONInventor: Kazuhiro Asada
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Publication number: 20200221619Abstract: A control system of a tape feeder that includes a reel on which is wound component supply tape, and a tape feeding device configured to draw out the component supply tape from the reel to a component pickup position, the control system including a sensor configured to detect information relating to a remaining amount of the tape on the reel; and a motor control section configured to change an operation parameter of a motor that is a drive source of the tape feeding device based on the tape remaining amount information detected by the sensor. Specifically, the motor control section changes the operation parameter of the motor so as to reduce the motor torque as the tape remaining amount on the reel decreases, based on the tape remaining amount information detected by the sensor.Type: ApplicationFiled: August 25, 2017Publication date: July 9, 2020Applicant: FUJI CORPORATIONInventors: Toshiaki KONDO, Kazuhiro ASADA
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Publication number: 20190265749Abstract: In the case where multiple individual work devices respectively executing a sequence of multiple tasks are controlled in an integrated manner by an integrated control device, log analysis among the multiple individual work devices is difficult. One of four individual work devices transmits time inquiry signal to main integrated control device via serial communication cable. Main integrated control device returns the time at time at which time inquiry signal was received to the one of four individual work devices to which time inquiry signal was transmitted. One of four individual work devices receives a reply from main integrated control device at time, adds the communication time to the time at time, and calculates the time at time. One of four individual work devices starts the calculation of the in-device time from calculated time as a starting point. One of four individual work devices logs based on in-device time.Type: ApplicationFiled: July 28, 2016Publication date: August 29, 2019Applicant: FUJI CORPORATIONInventor: Kazuhiro ASADA
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Patent number: 10064320Abstract: A component mounter which picks components which are stored in tape and supplied from a component supply device by a component picking device and mounts components on a board which is conveyed by a board conveyance device including a waste box which stores the cut tape after the components are picked, a scraping out device which can scrape the tape out of the waste box, and a control device which controls scraping out the stored tape by the scraping out device when the tape is stored in the waste box to a predetermined amount.Type: GrantFiled: July 2, 2012Date of Patent: August 28, 2018Assignee: FUJI CORPORATIONInventors: Hidetoshi Kawai, Masafumi Amano, Katsushi Ota, Kazuhiro Asada, Tsutomu Kunihiro
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Publication number: 20150208561Abstract: A component mounter which picks components which are stored in tape and supplied from a component supply device by a component picking device and mounts components on a board which is conveyed by a board conveyance device including a waste box which stores the cut tape after the components are picked, a scraping out device which can scrape the tape out of the waste box, and a control device which controls scraping out the stored tape by the scraping out device when the tape is stored in the waste box to a predetermined amount.Type: ApplicationFiled: July 2, 2012Publication date: July 23, 2015Applicant: FUJI MACHINE MFG. CO., LTDInventors: Hidetoshi Kawai, Masafumi Amano, Katsushi Ota, Kazuhiro Asada, Tsutomu Kunihiro
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Patent number: 8723242Abstract: A non-volatile semiconductor memory device and a method of manufacturing the same of the embodiments are provided. The non-volatile semiconductor memory device includes: drain contact plugs formed in memory cell regions and having bottom ends joined to drain diffusion layers of the respective memory cells; a local interconnect provided to extend in a WL direction across the memory cell regions and a shunt region, and having a bottom end joined commonly to plural source diffusion layers; drain via plugs formed in the memory cell regions and having bottom ends joined to the top ends of the respective drain contact plugs; and a power supply via for source formed in the shunt region to extend in a BL direction, and having a bottom end joined to the top end of the local interconnect.Type: GrantFiled: March 25, 2011Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Kazuhiro Asada
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Patent number: 8310082Abstract: An electrical junction box that includes a switching device such as a FET can prevent a ground potential on a circuit board from being indefinite and provides a power distribution unit utilizing the electrical junction box.Type: GrantFiled: September 1, 2009Date of Patent: November 13, 2012Assignee: Sumitomo Wiring Systems, Ltd.Inventor: Kazuhiro Asada
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Publication number: 20110233618Abstract: A non-volatile semiconductor memory device and a method of manufacturing the same of the embodiments are provided. The non-volatile semiconductor memory device includes: drain contact plugs formed in memory cell regions and having bottom ends joined to drain diffusion layers of the respective memory cells; a local interconnect provided to extend in a WL direction across the memory cell regions and a shunt region, and having a bottom end joined commonly to plural source diffusion layers; drain via plugs formed in the memory cell regions and having bottom ends joined to the top ends of the respective drain contact plugs; and a power supply via for source formed in the shunt region to extend in a BL direction, and having a bottom end joined to the top end of the local interconnect.Type: ApplicationFiled: March 25, 2011Publication date: September 29, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazuhiro ASADA
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Patent number: 7977731Abstract: A NOR flash memory has a plurality of memory cell transistors, wherein each memory cell transistor shares the source diffusion layer with another memory cell transistor adjacent thereto on one side thereof in the column direction and shares the drain diffusion layer with another memory cell transistor adjacent thereto on the other side thereof in the column direction, and the width of the source diffusion layer in the column direction is narrower than the width of the drain diffusion layer in the column direction.Type: GrantFiled: December 17, 2008Date of Patent: July 12, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Asada, Hideyuki Yamawaki
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Patent number: 7978459Abstract: To provide an electrical junction box that has a simple construction and an improved waterproof capability. An electrical junction box 10 comprises a circuit casing 30 and a circuit board 20 contained in the circuit casing. The circuit casing includes two cover bodies 31 and 51, which are opposite each other and include base plate sections 32 and 52 and peripheral walls 41 and 61 provided on the base plate sections. Portions of the peripheral walls 41 and 61 are cut off to define drainage apertures 45 and 65, which is oriented downwards. Bus bars B to be electrically connected to electrical conductive paths on the circuit board 20 are insert-molded in connectors 110 to 160 and arranged downward. Contacting portion K between the peripheral walls 41 and 61 is sealed through the entire periphery with the exception of the drainage aperture 45.Type: GrantFiled: March 24, 2009Date of Patent: July 12, 2011Assignee: Sumitomo Wiring Systems, Ltd.Inventors: Ryuji Nakanishi, Kazuhiro Asada
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Patent number: 7944681Abstract: This invention provides an electrical junction box that can restrain a temperature from increasing in a casing. An electrical junction box comprises a casing made of a synthetic resin material, a circuit board contained in the casing, semiconductor relay mounted on the circuit board, a bus bar. The bus bar is insert-molded in the casing. The bus bar includes an embedment section embedded in the casing, and a connecting section that is not embedded in the casing and thermally connected to the semiconductor relay.Type: GrantFiled: March 24, 2009Date of Patent: May 17, 2011Assignee: Sumitomo Wiring System, Ltd.Inventors: Ryuji Nakanishi, Kazuhiro Asada
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Publication number: 20100112831Abstract: An electrical junction box that includes a switching device such as a FET can prevent a ground potential on a circuit board from being indefinite and provides a power distribution unit utilizing the electrical junction box.Type: ApplicationFiled: September 1, 2009Publication date: May 6, 2010Applicant: SUMITOMO WIRING SYSTEMS, LTD.Inventor: Kazuhiro Asada
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Patent number: 7659670Abstract: A headlamp control circuit reduces a possibility that all headlamps become lights-out in a two-lamp system headlight, even if a switching element fails under a high-beam condition while the single switching element is driven to light two right and left high-beam filaments. A headlamp control circuit includes switch sections (SW1) and (SW2) for lighting low-beam filaments (21) and (31), a switch section (SW3) for lighting high-beam filaments (22) and (32) together, a diode (D1) for detecting an output voltage on the switch section SW3, and a control section (120) for turning the switch section (SW3) to an on-condition in the case where a high-beam indication is accepted and for turning the switch sections (SW1) and (SW2) to an on-condition in the case where a low-beam indication is accepted and in the case where a high-beam indication is accepted and the diode (D1) detects no high-beam lighting voltage.Type: GrantFiled: August 22, 2007Date of Patent: February 9, 2010Assignee: Sumitomo Wiring Systems, Ltd.Inventor: Kazuhiro Asada
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Publication number: 20090298311Abstract: To provide an electrical junction box that has a simple construction and an improved waterproof capability. An electrical junction box 10 comprises a circuit casing 30 and a circuit board 20 contained in the circuit casing. The circuit casing includes two cover bodies 31 and 51, which are opposite each other and include base plate sections 32 and 52 and peripheral walls 41 and 61 provided on the base plate sections. Portions of the peripheral walls 41 and 61 are cut off to define drainage apertures 45 and 65, which is oriented downwards. Bus bars B to be electrically connected to electrical conductive paths on the circuit board 20 are insert-molded in connectors 110 to 160 and arranged downward. Contacting portion K between the peripheral walls 41 and 61 is sealed through the entire periphery with the exception of the drainage aperture 45.Type: ApplicationFiled: March 24, 2009Publication date: December 3, 2009Applicant: SUMITOMO WIRING SYSTEMS, LTD.Inventors: Ryuji Nakanishi, Kazuhiro Asada
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Publication number: 20090294172Abstract: This invention provides an electrical junction box that can restrain a temperature from increasing in a casing. An electrical junction box 10 comprises a casing 11 made of a synthetic resin material, a circuit board 12 contained in the casing 11, semiconductor relays 32 mounted on the circuit board 12, a first bud bar 34, and a second bus bar 38. Both bud bars 34, 38 are insert-molded in the casing 11. The respective bus bars 34 and 38 include embedment sections 35A and 35B embedded in the casing 11, connecting sections 36A and 36B exposed from the casing 11 and thermally connected to the semiconductor relays 32.Type: ApplicationFiled: March 24, 2009Publication date: December 3, 2009Applicant: SUMITOMO WIRING SYSTEMS, LTD.Inventors: Ryuji Nakanishi, Kazuhiro Asada
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Publication number: 20090159956Abstract: A NOR flash memory has a plurality of memory cell transistors, wherein each memory cell transistor shares the source diffusion layer with another memory cell transistor adjacent thereto on one side thereof in the column direction and shares the drain diffusion layer with another memory cell transistor adjacent thereto on the other side thereof in the column direction, and the width of the source diffusion layer in the column direction is narrower than the width of the drain diffusion layer in the column direction.Type: ApplicationFiled: December 17, 2008Publication date: June 25, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Kazuhiro Asada, Hideyuki Yamawaki
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Publication number: 20090001888Abstract: A headlamp control circuit reduces a possibility that all headlamps become lights-out in a two-lamp system headlight, even if a switching element fails under a high-beam condition while the single switching element is driven to light two right and left high-beam filaments. A headlamp control circuit includes switch sections (SW1) and (SW2) for lighting low-beam filaments (21) and (31), a switch section (SW3) for lighting high-beam filaments (22) and (32) together, a diode (D1) for detecting an output voltage on the switch section SW3, and a control section (120) for turning the switch section (SW3) to an on-condition in the case where a high-beam indication is accepted and for turning the switch sections (SW1) and (SW2) to an on-condition in the case where a low-beam indication is accepted and in the case where a high-beam indication is accepted and the diode (D1) detects no high-beam lighting voltage.Type: ApplicationFiled: August 22, 2007Publication date: January 1, 2009Applicant: Sumitomo Wiring Systems, Ltd.Inventor: Kazuhiro Asada
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Patent number: 7377698Abstract: In an optical connector 1, a cord receiving hole portion 11c, where an optical fiber cord 90 can be inserted and received axially of the optical fiber cord, is formed in a housing 10. A mounting hole 13, through which a stopper 40 can be inserted into the portion 11c perpendicularly to an insertion direction of the cord 90, is formed in the housing. A positioning slit 42, having a width slightly smaller than the diameter of the cord 90, is formed in each plate-like portion 41. A blade portion 43 with an angle 90° is formed at each open end of the slit 42. When the stopper 40 is inserted into the portion 11c through the hole 13, each portion 43 abuts against a covering portion 92, and penetrates into the portion 92 while forcing a cut portion of this portion 92 away in the stopper insertion direction.Type: GrantFiled: July 9, 2001Date of Patent: May 27, 2008Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.Inventor: Kazuhiro Asada
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Patent number: 7327203Abstract: A PWM signal generation circuit and a PWM control circuit are provided in which the duty ratio is easily changed and which can also avoid adverse impact from ambient temperature changes and the like. At the beginning of charging a capacitor with a current flow, a voltage level at a connection point between the negative input terminal of a comparator and the capacitor is still below a charging threshold. When the charging threshold is exceeded, the comparator is inverted to a low state and a current flows into an output point of the comparator to start discharging the capacitor. At the beginning of discharging from the capacitor, the voltage level at the connection point is still above the discharging threshold. However, when the voltage level falls below the discharging threshold, the comparator returns to a high state, and the charging operation again takes over.Type: GrantFiled: November 8, 2005Date of Patent: February 5, 2008Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.Inventor: Kazuhiro Asada