Patents by Inventor Kazuhiro Iizuka

Kazuhiro Iizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10729926
    Abstract: The method for detoxifying asbestos disclosed here includes: preparing an asbestos-containing substance that contains at least one type of asbestos; preparing an asbestos treatment agent that contains a mineral acid, N-methyl-2-pyrrolidone and a fluoride; and bringing the asbestos-containing substance into contact with the asbestos treatment agent so as to detoxify asbestos in the asbestos-containing substance. Due to this configuration, asbestos in the asbestos-containing substance can be favorably detoxified.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: August 4, 2020
    Assignees: KOKIGUMI CO., LTD., NATIONAL UNIVERSITY CORPORATION TOTTORI UNIVERSITY
    Inventors: Toshimitsu Myoga, Koichi Takahashi, Kazuhiro Iizuka, Yuhei Matsubara, Toshiyuki Tanaka, Hisaki Okamoto
  • Patent number: 10722742
    Abstract: The method for detoxifying asbestos disclosed here includes: preparing an asbestos-containing substance that contains at least one type of asbestos; preparing an asbestos treatment agent that contains a mineral acid and N-methyl-2-pyrrolidone; and bringing the asbestos-containing substance into contact with the asbestos treatment agent so as to detoxify asbestos in the asbestos-containing substance. Due to this configuration, asbestos in the asbestos-containing substance can be favorably detoxified.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 28, 2020
    Assignees: KOKIGUMI CO., LTD, NATIONAL UNIVERSITY CORPORATION TOTTORI UNIVERSITY
    Inventors: Toshimitsu Myoga, Koichi Takahashi, Kazuhiro Iizuka, Yuhei Matsubara, Toshiyuki Tanaka, Hisaki Okamoto
  • Publication number: 20190374805
    Abstract: The method for detoxifying asbestos disclosed here includes: preparing an asbestos-containing substance that contains at least one type of asbestos; preparing an asbestos treatment agent that contains a mineral acid and N-methyl-2-pyrrolidone; and bringing the asbestos-containing substance into contact with the asbestos treatment agent so as to detoxify asbestos in the asbestos-containing substance. Due to this configuration, asbestos in the asbestos-containing substance can be favorably detoxified.
    Type: Application
    Filed: July 6, 2018
    Publication date: December 12, 2019
    Applicants: KOKIGUMI CO., LTD, NATIONAL UNIVERSITY CORPORATION TOTTORI UNIVERSITY
    Inventors: Toshimitsu MYOGA, Koichi TAKAHASHI, Kazuhiro IIZUKA, Yuhei MATSUBARA, Toshiyuki TANAKA, Hisaki OKAMOTO
  • Publication number: 20190358480
    Abstract: The method for detoxifying asbestos disclosed here includes: preparing an asbestos-containing substance that contains at least one type of asbestos; preparing an asbestos treatment agent that contains a mineral acid, N-methyl-2-pyrrolidone and a fluoride; and bringing the asbestos-containing substance into contact with the asbestos treatment agent so as to detoxify asbestos in the asbestos-containing substance. Due to this configuration, asbestos in the asbestos-containing substance can be favorably detoxified.
    Type: Application
    Filed: July 6, 2018
    Publication date: November 28, 2019
    Applicants: KOKIGUMI CO., LTD, KOKIGUMI CO., LTD, NATIONAL UNIVERSITY CORPORATION TOTTORI UNIVERSITY, NATIONAL UNIVERSITY CORPORATION TOTTORI UNIVERSITY
    Inventors: Toshimitsu MYOGA, Koichi TAKAHASHI, Kazuhiro IIZUKA, Yuhei MATSUBARA, Toshiyuki TANAKA, Hisaki OKAMOTO
  • Patent number: 10019793
    Abstract: According to an embodiment, A test system includes: a moving unit configured to move a test object, the test object including a first surface, a mark being printed on the first surface; a first imaging device configured to photograph the first surface of test object to obtain a first image; a cutter configured to scratch the first surface; a first unit configured to attach a tape to the first surface; a second unit configured to detach the tape from the first surface; a second imaging device configured to photograph the first surface after detaching the tape to obtain a second image; and a controller configured to compare the first image and the second image to output a comparison result.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: July 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Iizuka, Kohei Noma
  • Publication number: 20150279015
    Abstract: According to an embodiment, A test system includes: a moving unit configured to move a test object, the test object including a first surface, a mark being printed on the first surface; a first imaging device configured to photograph the first surface of test object to obtain a first image; a cutter configured to scratch the first surface; a first unit configured to attach a tape to the first surface; a second unit configured to detach the tape from the first surface; a second imaging device configured to photograph the first surface after detaching the tape to obtain a second image; and a controller configured to compare the first image and the second image to output a comparison result.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 1, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro IIZUKA, Kohei NOMA
  • Publication number: 20150070043
    Abstract: A method of inspecting a semiconductor device in which a plurality of conductive members is stacked includes drilling through the conductive layers using a drill and, while drilling, monitoring a probe device that is electrically connected to one of the conductive layers. When an electrical connection is established between the drill and probe device, the drilling is halted and said one of the conductive layers is inspected.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomokazu NAKAI, Kazuhiro IIZUKA
  • Publication number: 20150064876
    Abstract: A separating device separates a chip mounted on a substrate through a connecting material, from the substrate. The separating device includes a heating unit that heats the substrate at a temperature less than a melting point of the connecting material.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazuhiro IIZUKA
  • Patent number: 7833836
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: November 16, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Takyu, Kazuhiro Iizuka, Mika Kiritani
  • Publication number: 20090111218
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Application
    Filed: December 31, 2008
    Publication date: April 30, 2009
    Inventors: Shinya TAKYU, Kazuhiro Iizuka, Mika Kiritani
  • Patent number: 7482695
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: January 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Takyu, Kazuhiro Iizuka, Mika Kiritani
  • Publication number: 20070262445
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Application
    Filed: July 13, 2007
    Publication date: November 15, 2007
    Inventors: Shinya Takyu, Kazuhiro Iizuka, Mika Kiritani
  • Patent number: 7285864
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: October 23, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Takyu, Kazuhiro Iizuka, Mika Kiritani
  • Publication number: 20050179127
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Application
    Filed: July 15, 2004
    Publication date: August 18, 2005
    Inventors: Shinya Takyu, Kazuhiro Iizuka, Mika Kiritani
  • Publication number: 20050026326
    Abstract: A manufacturing method of a semiconductor device to electrically connect a semiconductor chip and a wiring board via a first bump electrode, at least one of the semiconductor chip and the wiring board having a second bump electrode or a connection electrode, the method includes: collectively performing flip chip bonding of the semiconductor chip to the wiring board and resin sealing processing between the semiconductor chip and the wiring board; wherein the collective processing includes controlling viscosity of a sealing resin with ultrasonic vibration so that the first bump electrode penetrates the sealing resin; and using the ultrasonic vibration to electrically connect the first bump electrode to the second bump electrode when at least one of the semiconductor chip and the wiring board has the second bump electrode, or using the ultrasonic vibration to electrically connect the first bump electrode to the connection electrode when at least one of the semiconductor chip and the wiring board has the connecti
    Type: Application
    Filed: May 12, 2004
    Publication date: February 3, 2005
    Inventors: Mika Kiritani, Shinya Takyu, Kazuhiro Iizuka
  • Patent number: 6838316
    Abstract: A bump is formed on at least one of a semiconductor chip and printed circuit board. A sealing material is applied to the surface of one of the semiconductor chip and printed circuit board. The printed circuit board is flip-chip-connected to the semiconductor chip via the sealing material while ultrasonic waves are applied to the printed circuit board to promote bonding by the bump.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: January 4, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Iizuka, Shinya Takyu
  • Publication number: 20030180986
    Abstract: A bump is formed on at least one of a semiconductor chip and printed circuit board. A sealing material is applied to the surface of one of the semiconductor chip and printed circuit board. The printed circuit board is flip-chip-connected to the semiconductor chip via the sealing material while ultrasonic waves are applied to the printed circuit board to promote bonding by the bump.
    Type: Application
    Filed: March 5, 2003
    Publication date: September 25, 2003
    Inventors: Kazuhiro Iizuka, Shinya Takyu
  • Patent number: D554084
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: October 30, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuhiro Iizuka