Portion of a semiconductor apparatus mounting-position accuracy measurement jig

- Kabushiki Kaisha Toshiba
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Description

FIG. 1 is a front, top and right side perspective view of a portion of a semiconductor apparatus mounting-position accuracy measurement jig, showing my new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 Is a right side elevational view thereof;

FIG. 5 is a left side elevational view thereof;

FIG. 6 is a top plan view thereof; and,

FIG. 7 Is a bottom plan view thereof.

The broken lines are for illustrative purposes only and form no part of the claimed design.

Claims

The ornamental design for a portion of a semiconductor apparatus mounting-position accuracy measurement jig, as shown and described.

Referenced Cited
U.S. Patent Documents
4629882 December 16, 1986 Matsuda et al.
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4877951 October 31, 1989 Muro
4887140 December 12, 1989 Wang
5414519 May 9, 1995 Han
6429387 August 6, 2002 Kuribayashi et al.
6459109 October 1, 2002 Takeshita et al.
20020179329 December 5, 2002 Fukuoka et al.
20050070068 March 31, 2005 Kobayashi
20050161836 July 28, 2005 Yudasaka et al.
20060270179 November 30, 2006 Yang
Foreign Patent Documents
D1242298 June 2005 JP
Patent History
Patent number: D554084
Type: Grant
Filed: Oct 31, 2005
Date of Patent: Oct 30, 2007
Assignee: Kabushiki Kaisha Toshiba
Inventor: Kazuhiro Iizuka (Yokohama)
Primary Examiner: Selina Sikder
Attorney: Banner & Witcoff, Ltd.
Application Number: 29/241,655