Patents by Inventor Kazuhiro Kashiwakura
Kazuhiro Kashiwakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210378090Abstract: The present invention addresses providing an electromagnetic wave reducing structure that can reduce leakage to outside of noise that is emitted by a circuit, from low frequency to high frequency, without using a special, difficult to obtain item. To address this problem, the electromagnetic wave reducing structure is provided with: a first conductor layer and a second conductor layer facing opposite each other; and a capacitor group comprising a plurality of capacitors connected to the first conductor layer and the second conductor layer. All the gaps are approximately equal between the capacitors in any pair of adjacent capacitors in a first direction within the plane and any pair of adjacent capacitors in a second direction which is the direction within the plane that is approximately perpendicular to the first direction, in a surface parallel to the surface of the first conductor layer that faces opposite the second conductor layer.Type: ApplicationFiled: August 7, 2017Publication date: December 2, 2021Applicant: NEC CorporationInventor: Kazuhiro KASHIWAKURA
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Publication number: 20210185805Abstract: A printed wiring board comprises: an insulation layer configured by a glass cloth in which fiber is woven, and a resin with which the glass cloth is impregnated; first wiring configured by a first line, a second line, and a third line; and second wiring configuring by a fourth line, a fifth line, and a sixth line, wherein a line length of the first line and a line length of the second line are equal to each other, a line length of the fifth line and a line length of the sixth line are equal to each other, a line length of the fourth line and the fifth line and a line length of the first line and the second line are equal to each other, and a line length of the first wiring and a line length of the second wiring are equal to each other.Type: ApplicationFiled: March 14, 2017Publication date: June 17, 2021Applicant: NEC CorporationInventor: Kazuhiro KASHIWAKURA
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Patent number: 10896872Abstract: The present invention addresses the problem of providing a connecting structure or similar that can minimize a decrease in a wireable region of a substrate while reducing the effect of stubs of a pair of vias on the output of a capacitor that is connected to said vias. In order to solve this problem, this connecting structure comprises: a first conductor that passes through a substrate and is provided with a first input/output section; a second conductor that passes through the substrate and is provided with a second input/output section; a first capacitor, one terminal of which being connected to a terminal of the first conductor that is on a first surface of the substrate, the other terminal of which being connected to a terminal of the second conductor that is on the first surface of the substrate; and a second capacitor or a resistor.Type: GrantFiled: September 15, 2017Date of Patent: January 19, 2021Assignee: NEC CORPORATIONInventors: Ayako Uemura, Kazuhiro Kashiwakura
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Publication number: 20190357350Abstract: The present invention addresses the problem of reducing a delay time difference between signals transmitted by means of a differential signal wires in a wiring board having glass cloth. A wiring board comprises: an insulating layer which includes fibers having a planar shape with translational symmetry with respect to two linearly independent, predetermined translational vectors, and a layer-like insulating material encapsulating the fibers; and through-holes formed at the starting and end points of a vector which is the sum of substantially integral multiples of the two translational vectors and which has the starting point on the planar shape.Type: ApplicationFiled: February 28, 2018Publication date: November 21, 2019Applicant: NEC CorporationInventor: Kazuhiro KASHIWAKURA
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Publication number: 20190252310Abstract: The present invention addresses the problem of providing a connecting structure or similar that can minimize a decrease in a wireable region of a substrate while reducing the effect of stubs of a pair of vias on the output of a capacitor that is connected to said vias. In order to solve this problem, this connecting structure comprises: a first conductor that passes through a substrate and is provided with a first input/output section; a second conductor that passes through the substrate and is provided with a second input/output section; a first capacitor, one terminal of which being connected to a terminal of the first conductor that is on a first surface of the substrate, the other terminal of which being connected to a terminal of the second conductor that is on the first surface of the substrate; and a second capacitor or a resistor.Type: ApplicationFiled: September 15, 2017Publication date: August 15, 2019Applicant: NEC CorporationInventors: Ayako UEMURA, Kazuhiro KASHIWAKURA
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Patent number: 10375818Abstract: An objective of the present invention is to provide a printed board being capable of suppressing EMI emissions from power supply wirings. To accomplish the objective, a printed board of the present invention includes a plurality of ground layers disposed in a printed board, a power supply layer put between the plurality of the ground layers, and through holes disposed along at least periphery of the printed board and connecting the plurality of the ground layers, wherein the through holes are disposed at intervals according to a wavelength corresponding to a maximum frequency of electromagnetic waves to be suppressed.Type: GrantFiled: July 4, 2016Date of Patent: August 6, 2019Assignee: NEC CORPORATIONInventors: Kazuhiro Kashiwakura, Ayako Uemura
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Patent number: 10250215Abstract: There has been a problem of generating anti-resonance between a three-terminal capacitor and a capacitor when the three-terminal capacitor and the capacitor are mounted. In order to solve the problem, this electronic circuit includes: a capacitor and a three-terminal capacitor, which are connected to a power supply terminal of a circuit component, and a power supply, and which are connected in parallel to each other between the power supply and ground; and a resistor that is connected in series between the ground and a ground terminal of the three-terminal capacitor and/or the capacitor.Type: GrantFiled: December 8, 2015Date of Patent: April 2, 2019Assignee: NEC CORPORATIONInventor: Kazuhiro Kashiwakura
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Publication number: 20180235076Abstract: An objective of the present invention is to provide a printed board being capable of suppressing EMI emissions from power supply wirings. To accomplish the objective, a printed board of the present invention includes a plurality of ground layers disposed in a printed board, a power supply layer put between the plurality of the ground layers, and through holes disposed along at least periphery of the printed board and connecting the plurality of the ground layers, wherein the through holes are disposed at intervals according to a wavelength corresponding to a maximum frequency of electromagnetic waves to be suppressed.Type: ApplicationFiled: July 4, 2016Publication date: August 16, 2018Applicant: NEC CorporationInventors: Kazuhiro KASHIWAKURA, Ayako UEMURA
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Publication number: 20180184516Abstract: An objective of the present invention is to provide a printed board capable of suppressing EMI emissions from an electric cable. To accomplish the objective, the present invention is a printed board including a signal wiring to which an electric cable is connected, the printed board including: ground layers above and below the signal wiring put on upper and lower sides of the signal wiring to which the electric cable is connected; and a plurality of through holes connecting the ground layers above and below the signal wiring, wherein the plurality of the through holes are disposed at and near the signal wiring and are spaced apart at intervals according to a wavelength corresponding to a maximum frequency of electromagnetic waves to be suppressed.Type: ApplicationFiled: July 4, 2016Publication date: June 28, 2018Applicant: NEC CorporationInventors: Kazuhiro KASHIWAKURA, Ayako UEMURA
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Patent number: 9980370Abstract: To provide a printed board that solves the problem of transmission characteristics deterioration, the disclosed printed board includes a substrate, a circular signal pad that is provided on the substrate, a doughnut-shaped ground pad, which sandwiches the substrate that surrounds, in a doughnut shape, the signal pad, and which surrounds the outer circumference of the substrate, and one or more recessed sections that are disposed on the substrate that surrounds, in the doughnut shape, the signal pad.Type: GrantFiled: September 11, 2014Date of Patent: May 22, 2018Assignee: NEC CORPORATIONInventor: Kazuhiro Kashiwakura
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Publication number: 20180014402Abstract: [Problem] To achieve a wiring board capable of suppressing the difference in the amount of delay between two signal wirings constituting differential signal wirings, while securing flexibility in design. [Solution] A wiring board is configured to include a first insulating layer 1, a first signal wiring 2 and a second signal wiring 3. The first insulating layer 1 includes fibers 4 having the long axis in a first direction and aligned approximately parallel to each other at a first interval and an insulating material 5 filling gaps between the fibers 4 of the first direction. The first signal wiring 2 is formed approximately parallel to the first direction on the first insulating layer 1. The second signal wiring 3 is formed parallel to the first signal wiring 2 such that the interval between the first and second signal wirings 2 and 3 be approximately an integral multiple of the first interval, and the second signal wiring 3 transmits a differential signal of a signal transmitted on the first signal wiring 2.Type: ApplicationFiled: January 15, 2016Publication date: January 11, 2018Applicant: NEC CorporationInventor: Kazuhiro KASHIWAKURA
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Patent number: 9859603Abstract: A printed wiring board is provided with a wiring layer, a first ground layer, a second ground layer, a grounding through-hole, a signal through-hole, a first clearance, and a second clearance. The wiring layer has a signal line. The first ground layer has a first ground plane. The second ground layer is positioned between the wiring layer and the first ground layer and has a second ground plane. The grounding through-hole passes through the wiring layer, the first ground layer, and the second ground layer and is connected to the second ground plane. The signal through-hole passes through the wiring layer, the first ground layer, and the second ground layer and is connected to the signal line. The first clearance is formed in the first ground layer, is positioned in the vicinity of the signal through-hole and the grounding through-hole, and separates the first ground plane from the signal through-hole and the grounding through-hole.Type: GrantFiled: January 8, 2014Date of Patent: January 2, 2018Assignee: NEC CorporationInventor: Kazuhiro Kashiwakura
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Publication number: 20170323729Abstract: There has been a problem of generating anti-resonance between a three-terminal capacitor and a capacitor when the three-terminal capacitor and the capacitor are mounted. In order to solve the problem, this electronic circuit includes: a capacitor and a three-terminal capacitor, which are connected to a power supply terminal of a circuit component, and a power supply, and which are connected in parallel to each other between the power supply and ground; and a resistor that is connected in series between the ground and a ground terminal of the three-terminal capacitor and/or the capacitor.Type: ApplicationFiled: December 8, 2015Publication date: November 9, 2017Applicant: NEC CorporationInventor: KAZUHIRO KASHIWAKURA
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Patent number: 9603275Abstract: The present invention is a backplane board including a first circuit board, a second circuit board, a first slot in which a first connector is connected with the first circuit board, and a second slot in which a second connector is connected with the second circuit board. The first connector and the second connector are arranged so that pin arrangement of the first connector may be shifted by at least one column in a longitudinal direction against pin arrangement of the second connector.Type: GrantFiled: March 13, 2013Date of Patent: March 21, 2017Assignee: NEC CORPORATIONInventor: Kazuhiro Kashiwakura
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Patent number: 9532442Abstract: Provided is a feed line structure that enables suppression of noise entering a primary power supply from an electronic circuit without using a circuit component such as a choke coil and a capacitor and also without increasing an occupied area on the circuit board, so that an EMI countermeasure is achieved. The feed line structure includes a feed line composed by pairing a power supply wire 41 and a reference potential wire 42 in an insulator 40, and is characterized in that a wire 43 in a floating state in potential is provided.Type: GrantFiled: June 17, 2010Date of Patent: December 27, 2016Assignee: NEC CORPORATIONInventor: Kazuhiro Kashiwakura
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Patent number: 9433094Abstract: An electronic substrate 100 includes: a substrate member 110 which has a shape of plane plate and whose pair of main surfaces 110a and 110b are opposite each other; a plurality of connection terminals 130 which are formed so as to be arranged on an edge side of the substrate member 110 and on at least one surface out of the pair of main surfaces 110a and 110b of the substrate member 110; a plurality of wirings 120 which are connected with the plural connection terminals 130; and a plurality of openings 140A arranged in an area, which exists between connection terminals 130 adjacent each other out of the plural connection terminals 130 and in which the connection terminals 130 adjacent each other extend, in an extending direction of the connection terminals 130 adjacent each other.Type: GrantFiled: December 11, 2013Date of Patent: August 30, 2016Assignee: NEC CORPORATIONInventor: Kazuhiro Kashiwakura
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Patent number: 9397418Abstract: The present invention provides a system and a method which enable an increase in signal transmission speed and stable operation, without incurring the likes of restrictions on the manufacturing of circuit boards. A transmission system includes an AC terminal connector, having an AC termination circuit including a resistor and a capacitor, at the open ends of through hole stubs provided in a circuit board.Type: GrantFiled: March 30, 2012Date of Patent: July 19, 2016Assignee: NEC CORPORATIONInventor: Kazuhiro Kashiwakura
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Publication number: 20160205768Abstract: To provide a printed board that solves the problem of transmission characteristics deterioration, the disclosed printed board includes a substrate, a circular signal pad that is provided on the substrate, a doughnut-shaped ground pad, which sandwiches the substrate that surrounds, in a doughnut shape, the signal pad, and which surrounds the outer circumference of the substrate, and one or more recessed sections that are disposed on the substrate that surrounds, in the doughnut shape, the signal pad.Type: ApplicationFiled: September 11, 2014Publication date: July 14, 2016Inventor: Kazuhiro KASHIWAKURA
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Patent number: 9380704Abstract: A through-hole stub AC termination circuit including a resistor and a capacitor, is connected to an open end of a stub of a through-hole provided in a circuit board.Type: GrantFiled: March 30, 2012Date of Patent: June 28, 2016Assignee: NEC CORPORATIONInventor: Kazuhiro Kashiwakura
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Patent number: 9265149Abstract: A printed wiring board comprises ground layers stacked via insulator(s); a first through hole; second through holes ; and signal wirings each extending from the first through hole through the clearance between predetermined ones of the ground layers, disposed between predetermined second through holes of the second through holes. Each of first clearances in the ground layers neighboring layer in which the signal wiring is disposed has an outline that a distance between the first through hole and outline of the first clearance is minimum of the signal wiring. Each of second clearances in the ground layers not adjacent to the signal wiring has an outline formed outside a circle connecting each center of second through holes centering the first signal through hole, such that outline of second clearance does not contact with the second through holes.Type: GrantFiled: April 9, 2012Date of Patent: February 16, 2016Assignee: NEC CORPORATIONInventor: Kazuhiro Kashiwakura