Abstract: A printed wiring board is provided with a wiring layer, a first ground layer, a second ground layer, a grounding through-hole, a signal through-hole, a first clearance, and a second clearance. The wiring layer has a signal line. The first ground layer has a first ground plane. The second ground layer is positioned between the wiring layer and the first ground layer and has a second ground plane. The grounding through-hole passes through the wiring layer, the first ground layer, and the second ground layer and is connected to the second ground plane. The signal through-hole passes through the wiring layer, the first ground layer, and the second ground layer and is connected to the signal line. The first clearance is formed in the first ground layer, is positioned in the vicinity of the signal through-hole and the grounding through-hole, and separates the first ground plane from the signal through-hole and the grounding through-hole.

Abstract: An electronic substrate 100 includes: a substrate member 110 which has a shape of plane plate and whose pair of main surfaces 110a and 110b are opposite each other; a plurality of connection terminals 130 which are formed so as to be arranged on an edge side of the substrate member 110 and on at least one surface out of the pair of main surfaces 110a and 110b of the substrate member 110; a plurality of wirings 120 which are connected with the plural connection terminals 130; and a plurality of openings 140A arranged in an area, which exists between connection terminals 130 adjacent each other out of the plural connection terminals 130 and in which the connection terminals 130 adjacent each other extend, in an extending direction of the connection terminals 130 adjacent each other.

Abstract: A decoupling circuit comprises an output buffer that includes a transistor, and a capacitor that has an end thereof connected to an output node of the output buffer and the other end thereof connected to a power supply line, and a logic level outputted by the output node of the output buffer is fixed.

Abstract: The present invention is a backplane board including a first circuit board, a second circuit board, a first slot in which a first connector is connected with the first circuit board, and a second slot in which a second connector is connected with the second circuit board. The first connector and the second connector are arranged so that pin arrangement of the first connector may be shifted by at least one column in a longitudinal direction against pin arrangement of the second connector.

Abstract: Disclosed is a method for design validity verification of an electronic circuit board with regard to power supply noise, wherein with regard to an i-th LSI (i=1 to n) on the electronic circuit board, an input voltage Vin[i] to the LSI from the printed circuit board is given by Vin[i]=VDD?Z1si[i]×VDD/(Z1si[i]+Z11[i]), where Z1si[i] is an input impedance characteristic and Z11[i] is a reflected impedance characteristic viewed from a position at which the i-th LSI is mounted, being a characteristic with the i-th LSI omitted from the whole of the electronic circuit board and a judgment is made as to whether or not a reflected voltage Vr[i]=Vin[i]×(Z1si[i]+Z11[i])/(Z1si[i]?Z11[i]) satisfies |Vr[i]|?? V (power supply variation tolerance range).

Abstract: A method includes: with a setting frequency set as an operating frequency of an LSI, selecting a capacitor having a lowest resonant impedance and a resonant frequency close to the setting frequency with reference to a capacitor characteristic database and installing one or more capacitors, each being the selected capacitor, as high frequency decoupling capacitors, the number thereof corresponding to a value obtained by dividing the upper limit of the power feeding line impedance by a resonant impedance of the capacitor.

Abstract: Provided is a printed wiring board including a power source, a plurality of LSIs, and a planar power supply wiring for supplying power from the power source to the LSIs. A plurality of partial wiring patterns each forming a current path from the power source to the LSIs are provided by forming gaps in the power supply wiring.

Abstract: A decoupling circuit comprises an output buffer that includes a transistor, and a capacitor that has an end thereof connected to an output node of the output buffer and the other end thereof connected to a power supply line, and a logic level outputted by the output node of the output buffer is fixed.

Abstract: A through-hole stub AC termination circuit including a resistor and a capacitor, is connected to an open end of a stub of a through-hole provided in a circuit board.

Abstract: A method includes: with a setting frequency set as an operating frequency of an LSI, selecting a capacitor having a lowest resonant impedance and a resonant frequency close to the setting frequency with reference to a capacitor characteristic database and installing one or more capacitors, each being the selected capacitor, as high frequency decoupling capacitors, the number thereof corresponding to a value obtained by dividing the upper limit of the power feeding line impedance by a resonant impedance of the capacitor.

Abstract: A transmission system includes an AC termination connector including an AC termination circuit including a resistor and a capacitor, at an open end of a stub of a through-hole provided in a circuit board.

Abstract: Provided is a printed wiring board including a power source, a plurality of LSIs, and a planar power supply wiring for supplying power from the power source to the LSIs. A plurality of partial wiring patterns each forming a current path from the power source to the LSIs are provided by forming gaps in the power supply wiring.

Abstract: Disclosed is a printed wiring board having signal layers each interposed between a power supply layer and a ground layer, wherein the signal layer includes at least one of a wiring region for a ground potential and a wiring region for a power supply potential.

Abstract: A printed wiring board includes ground layers stacked via insulator(s), a first through hole, second through holes and signal wirings, each signal wiring extending from the first through hole through the clearance between predetermined ones of the ground layers, and disposed between predetermined second through holes of the second through holes. Each of first clearances in the ground layers neighboring a layer in which the signal wiring is disposed has an outline such that a distance between the first through hole and outline of the first clearance is minimum of the signal wiring. Each of second clearances in the ground layers not adjacent to the signal wiring has an outline formed outside a circle connecting each center of second through holes centering the first signal through hole, such that the outline of second clearance does not contact with the second through holes.

Abstract: A printed wiring board comprises ground layers stacked via insulator(s); a first through hole; second through holes; and signal wirings each extending from the first through hole through the clearance between predetermined ones of the ground layers, disposed between predetermined second through holes of the second through holes. Each of first clearances in the ground layers neighboring layer in which the signal wiring is disposed has an outline that a distance between the first through hole and outline of the first clearance is minimum of the signal wiring. Each of second clearances in the ground layers not adjacent to the signal wiring has an outline formed outside a circle connecting each center of second through holes centering the first signal through hole, such that outline of second clearance does not contact with the second through holes.

Abstract: A printed wiring board suppresses characteristic impedance mismatch that occurs when the printed wiring board is equipped with a through-type coaxial connector, and includes ground layers stacked in a plurality of layers via insulating layers; a through-hole; a clearance serving as an anti-pad provided in an area between the through-hole and the ground layers; and signal wiring extending from the through-hole to between prescribed ones of the ground layers through the clearance. The prescribed ones of the ground layers have a wiring-impedance adjustment area for adjusting the impedance of the signal wiring, the wiring-impedance adjustment area being arranged so as to overlap a portion of the signal wiring in the clearance.

Abstract: Disclosed is a method of analyzing power supply noise including: extracting power supply and ground information as well as a capacitor and an LSI chip connected to a power supply and ground from electronic circuit design information; creating an analytical model of power supply noise by connecting respective models of the impedance characteristics of the capacitor and LSI chip to mounting positions of a board model; calculating reflected voltage at the LSI chip based on an impedance characteristic between the power supply of the LSI chip and ground; calculating power supply noise from the LSI chip to the electronic circuit board; based on the reflected voltage at the LSI chip.

Abstract: Provided is a feed line structure that enables suppression of noise entering a primary power supply from an electronic circuit without using a circuit component such as a choke coil and a capacitor and also without increasing an occupied area on the circuit board, so that an EMI countermeasure is achieved. The feed line structure includes a feed line composed by pairing a power supply wire 41 and a reference potential wire 42 in an insulator 40, and is characterized in that a wire 43 in a floating state in potential is provided.

Abstract: Disclosed is a method for design validity verification of an electronic circuit board with regard to power supply noise, wherein with regard to an i-th LSI (i=1 to n) on the electronic circuit board, an input voltage Vin[i] to the LSI from the printed circuit board is given by Vin[i]=VDD?Zlsi[i]×VDD/(Zlsi[i]+Z11[i]), where Zlsi[i] is an input impedance characteristic and Z11[i] is a reflected impedance characteristic viewed from a position at which the i-th LSI is mounted, being a characteristic with the i-th LSI omitted from the whole of the electronic circuit board and a judgment is made as to whether or not a reflected voltage Vr[i]=Vin[i]×(Zlsi[i]+Z11[i])/(Zlsi[i]?Z11[i]) satisfies |Vr[i]|??V (power supply variation tolerance range).

Abstract: Disclosed is a method for design validity verification of an electronic circuit board with regard to power supply noise, wherein with regard to an i-th LSI (i=1 to n) on the electronic circuit board, an input voltage Vin[i] to the LSI from the printed circuit board is given by Vin[i]=VDD?Z1si[i]×VDD/(Z1si[i]+Z11[i]),where Z1si[i] is an input impedance characteristic and Z11[i] is a reflected impedance characteristic viewed from a position at which the i-th LSI is mounted, being a characteristic with the i-th LSI omitted from the whole of the electronic circuit board and a judgment is made as to whether or not a reflected voltage Vr[i]=Vin[i]×(Z1si[i]+Z11[i])/(Z1si[i]?Z11[i]) satisfies |Vr[i]|?? V (power supply variation tolerance range).