Abstract: A method for producing molded foam articles that molds molded foam articles continuously, the method comprising continuously repeating the following step 1, step 2, step 3 and step 4 in this order; wherein step 1 comprises melting a resin composition that includes a liquid crystal polyester; step 2 comprises introducing, with an introduction device, a supercritical fluid that is unreactive, in a supercritical state, with the liquid crystal polyester, and is a gas at normal temperature and normal pressure, into the resin composition in an amount of at least 0.1 parts by mass but not more than 0.

Abstract: A resin composition is provided which includes a resin component, a fibrous filler, and a plate-like filler. With respect to 100 parts by mass of the resin component, the content of the fibrous filler is from 30 parts by mass or more to 100 parts by mass or less, the content of the plate-like filler is from 20 parts by mass or more to 80 parts by mass or less, and the total content of the fibrous filler and the plate-like filler is from 50 parts by mass or more to 180 parts by mass or less. The resin component includes an amorphous resin, and the content of the amorphous resin is from 60 parts by mass or more to 100 parts by mass or less.

Abstract: A method for producing molded foam articles that molds molded foam articles continuously, the method comprising continuously repeating the following step 1, step 2, step 3 and step 4 in this order; wherein step 1 comprises melting a resin composition that includes a liquid crystal polyester; step 2 comprises introducing, with an introduction device, a supercritical fluid that is unreactive, in a supercritical state, with the liquid crystal polyester, and is a gas at normal temperature and normal pressure, into the resin composition in an amount of at least 0.1 parts by mass but not more than 0.

Abstract: A resin composition is provided which includes a resin component, a fibrous filler, and a plate-like filler. With respect to 100 parts by mass of the resin component, the content of the fibrous filler is from 30 parts by mass or more to 100 parts by mass or less, the content of the plate-like filler is from 20 parts by mass or more to 80 parts by mass or less, and the total content of the fibrous filler and the plate-like filler is from 50 parts by mass or more to 180 parts by mass or less. The resin component includes an amorphous resin, and the content of the amorphous resin is from 60 parts by mass or more to 100 parts by mass or less.

Abstract: There is provided a 3-terminal negative differential resistance field effect element having a high output and high frequency characteristic, requiring low power consumption, and preferably having a high PVCR. The field effect element uses a compound hetero structure and forms a dual channel layer by connecting a high-transfer degree quantum well layer (13) to a low-transfer degree quantum dot layer (15) via a barrier layer (14) on a substrate (11). Under existence of an electric field obtained by voltage application to a gate electrode (17), the negative resistance field effect element (10) changes a carrier accelerated by a drain voltage applied to a drain electrode (19) from a high-transfer degree channel to a low-transfer degree channel by the tunnel effect or over the barrier layer, thereby exhibiting negative differential resistance for the drain current and changing the negative resistance inclination by the gate voltage.

Abstract: There is provided a 3-terminal negative differential resistance field effect element having a high output and high frequency characteristic, requiring low power consumption, and preferably having a high PVCR. The field effect element uses a compound hetero structure and forms a dual channel layer by connecting a high-transfer degree quantum well layer (13) to a low-transfer degree quantum dot layer (15) via a barrier layer (14) on a substrate (11). Under existence of an electric field obtained by voltage application to a gate electrode (17), the negative resistance field effect element (10) changes a carrier accelerated by a drain voltage applied to a drain electrode (19) from a high-transfer degree channel to a low-transfer degree channel by the tunnel effect or over the barrier layer, thereby exhibiting negative differential resistance for the drain current and changing the negative resistance inclination by the gate voltage.

Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

Abstract: A photonic crystal directional coupler composed of at least two linear defect waveguides introduced into a photonic crystal. The medium constant and the lattice constant of the photonic crystal at the photonic crystal directional coupling part, the sizes and shapes of the elements constituting the periodical structure of the photonic crystal are varied. Thereby the difference in propagation constant between the even and odd modes of the photonic crystal directional coupling part is increased, thus shortening the coupling length of the photonic crystal directional coupler.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

Abstract: A photonic crystal directional coupler composed of at least two linear defect waveguides introduced into a photonic crystal. The medium constant and the lattice constant of the photonic crystal at the photonic crystal directional coupling part, the sizes and shapes of the elements constituting the periodical structure of the photonic crystal are varied. Thereby the difference in propagation constant between the even and odd modes of the photonic crystal directional coupling part is increased, thus shortening the coupling length of the photonic crystal directional coupler.

Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.