Patents by Inventor Kazuhiro Komori

Kazuhiro Komori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device
    Patent number: 4652897
    Abstract: A semiconductor memory device wherein a portion of source region of a field-effect transistor that serves as a memory cell has a low impurity concentration, so that hot carriers generated on the source side are injected into the floating gate. Hot carriers are generated by utilizing a large electric field intensity established by the drop of voltage in the region of low impurity concentration. The voltage difference is so great between the source region and the control gate that hot carriers generated on the source side are efficiently injected into the floating gate.
    Type: Grant
    Filed: July 15, 1985
    Date of Patent: March 24, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Kousuke Okuyama, Kazuhiro Komori, Hisao Katto
  • Forming memory transistors with varying gate oxide thicknesses
    Patent number: 4651406
    Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.
    Type: Grant
    Filed: June 4, 1986
    Date of Patent: March 24, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Shimizu, Kazuhiro Komori, Yasunobu Kosa, June Sugiura
  • Semiconductor integrated circuit device with memory MISFETS and thin and thick gate insulator MISFETS
    Patent number: 4471373
    Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.
    Type: Grant
    Filed: January 7, 1981
    Date of Patent: September 11, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Shimizu, Kazuhiro Komori, Yasunobu Kosa, June Sugiura
  • Semiconductor memory device
    Patent number: 4451904
    Abstract: A semiconductor memory device includes a number of conductive layers for bit and selection lines alternately juxtaposed on the surface of a semiconductor substrate beneath a field insulating layer, with a number of MOS type memory cells arranged between the conductive layers for the bit and selection lines.
    Type: Grant
    Filed: January 26, 1981
    Date of Patent: May 29, 1984
    Assignee: Hitachi, Ltd.
    Inventors: June Sugiura, Yasunobu Kosa, Kazuhiro Komori, Ken Uchida, Shinji Shimizu
  • Method of manufacturing a semiconductor integrated circuit device
    Patent number: 4373249
    Abstract: A semiconductor integrated circuit device, especially an EPROM (Electrically Programmable Read Only Memory) device which consists of an MIS type memory transistor portion having a floating gate electrode and a control gate electrode on said floating gate electrode, and of an MIS type transistor portion having a gate electrode is formed by patterning the same conductor layer as the floating gate electrode in the periphery of said MIS type memory transistor portion.
    Type: Grant
    Filed: September 12, 1980
    Date of Patent: February 15, 1983
    Assignee: Hitachi, Ltd.
    Inventors: Yasunobu Kosa, Kazuhiro Komori