Abstract: An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.

Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines. The memory block MB and the data driver block DB are disposed adjacent to each other along the first direction D1.

Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1 when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is a direction D1 and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is a direction D2. At least one of the circuit blocks on both ends of the circuit blocks CB1 to CBN is a scan driver block for driving a scan line. Or, the scan driver block SB is disposed along the direction D1 on the side of the first to Nth circuit blocks in the direction D2.

Abstract: The liquid crystal display device of this invention includes a plurality of picture element regions each defined by a first electrode provided on a face of a first substrate facing a liquid crystal layer and a second electrode provided on a second substrate so as to oppose the first electrode via the liquid crystal layer sandwiched therebetween. In each of the picture element regions, the first electrode has a plurality of openings and a solid portion, the liquid crystal layer is in a vertical orientation state when no voltage is applied between the first electrode and the second electrode, and when a voltage is applied between the first electrode and the second electrode, a plurality of liquid crystal domains each in a radially-inclined orientation state are respectively formed in the plurality of openings and the solid portion by inclined electrode fields generated at respective edge portions of the openings of the first electrode.

Abstract: The liquid crystal display device of this invention includes a plurality of picture element regions each defined by a first electrode provided on a face of a first substrate facing a liquid crystal layer and a second electrode provided on a second substrate so as to oppose the first electrode via the liquid crystal layer sandwiched therebetween. In each of the picture element regions, the first electrode has a plurality of openings and a solid portion, the liquid crystal layer is in a vertical orientation state when no voltage is applied between the first electrode and the second electrode, and when a voltage is applied between the first electrode and the second electrode, a plurality of liquid crystal domains each in a radially-inclined orientation state are respectively formed in the plurality of openings and the solid portion by inclined electrode fields generated at respective edge portions of the openings of the first electrode.

Abstract: In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.

Abstract: A reference clock signal generation circuit for generating a reference clock signal for a charge-pump operation which raises or lowers a voltage includes a clock signal generation circuit which generates a reference clock signal having one of first to nth (n is an integer of two or more) frequencies, a wait time setting register in which a value corresponding to a wait time is set, and a frequency setting register in which a value corresponding to one of the first to nth frequencies is set. The clock signal generation circuit generates the reference clock signal having a predetermined frequency in a start period from start of the charge-pump operation to completion of the wait time, and generates the reference clock signal having a frequency corresponding to the value set in the frequency setting register in an operation period after the start period.

Abstract: An integrated circuit device includes: first to Nth circuit blocks CB1 to CBN disposed along a direction D1, the circuit blocks CB1 to CBN includes a data driver block DB. A data driver DR included in the data driver block DB includes Q driver cells DRC1 to DRCQ arranged along a direction D2, each of the driver cells outputting a data signal corresponding to image data for one pixel. When a width of each of the driver cells DRC1 to DRCQ in the direction D2 is WD, each of the circuit blocks CB1 to CBN has a width WB in the direction D2 of “Q×WD?WB<(Q+1)×WD”.

Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1, a first interface region provided on the D2 side of the circuit blocks CB1 to CBN, and a second interface region provided on the D4 side of the circuit blocks CB1 to CBN. The circuit blocks CB1 to CBN include a data driver block DB and a circuit block other than the data driver block DB. When the widths of the first interface region, the circuit blocks CB1 to CBN, and the second interface region in the direction D2 are respectively W1, WB, and W2, the integrated circuit device has a width W in the direction D2 of “W1+WB+W2?W<W1+2×WB+W2”.

Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a logic circuit block LB, a grayscale voltage generation circuit block GB, data driver blocks DB1 to DB4, and a power supply circuit block PB. The data driver blocks DB1 to DB4 are disposed between the logic circuit block LB and the grayscale voltage generation circuit block GB, and the power supply circuit block PB.

Abstract: The liquid crystal display device of the present invention includes a first substrate, a second substrate, and a vertical alignment type liquid crystal layer provided between the first substrate and the second substrate, and includes a plurality of picture element regions each defined by a first electrode provided on one side of the first substrate that is closer to the liquid crystal layer and a second electrode provided on the second substrate so as to oppose the first electrode via the liquid crystal layer. The first substrate includes a first orientation-regulating structure in each of the plurality of picture element regions, the first orientation-regulating structure exerting an orientation-regulating force so as to form a plurality of liquid crystal domains in the liquid crystal layer, each of the liquid crystal domains taking a radially-inclined orientation in the presence of an applied voltage.

Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a high-speed interface circuit block HB which transfers data through a serial bus using differential signals, and a circuit block other than HB. The high-speed interface circuit block HB is disposed as an Mth circuit block CBM (2?M?N?1) of the circuit blocks CB1 to CBN.

Abstract: An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects VSSL for supplying a first power supply voltage VSS to memory cells MC are formed in a metal interconnect layer in which a plurality of wordlines WL are formed; and wherein a plurality of second power supply interconnects VDDL for supplying a second power supply voltage VDD to the memory cells are formed in another metal interconnect layer in which a plurality of bitlines BL are formed, the second power supply voltage VDD being higher than the first power supply voltage VSS. A plurality of bitline protection interconnects SHD are formed in a layer above the bitlines BL, and each of the bitline protection interconnects SHD at least partially covers one of the bitlines BL in a plan view.

Abstract: An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects for supplying a first power supply voltage to a plurality of memory cells are provided in a metal interconnect layer in which a plurality of bitlines are formed; wherein a second power supply interconnect for supplying a second power supply voltage to the memory cells is provided in a metal interconnect layer in which a plurality of wordlines are formed, the second power supply voltage being higher than the first power supply voltage; wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is provided in a layer above the bitline protection interconnects, the third power supply voltage being

Abstract: An integrated circuit device, including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines; and the memory block MB includes a memory cell array, a row address decoder RD, and a sense amplifier block SAB.

Abstract: A driver circuit which drives a source line of an electro-optical device includes a source line driver section which supplies a grayscale voltage corresponding to grayscale data to the source line, a source output switch section which short-circuits the source line and a common line connected with a capacitor before the source line driver section drives the source line, and a charge recycle control section which controls the source output switch section. The charge recycle control section determines whether or not to short-circuit the source line and the common line in source line units based on the grayscale data and polarity of a common electrode voltage supplied to a common electrode opposite to a pixel electrode of the electro-optical device. The source output switch section short-circuits the source line and the common line based on the determination result of the charge recycle control section.

Abstract: A display driver includes a common electrode charge storage switch provided between a first capacitor element connection node to which one end of a first capacitor element can be connected and a common electrode voltage output node to which a voltage of a common electrode opposite to a pixel electrode of an electro-optical device through an electro-optical material is supplied, a source charge storage switch provided between a second capacitor element connection node to which one end of a second capacitor element can be connected and a source voltage output node to which a voltage of a source line of the electro-optical device is supplied, and a node short circuit switch provided between the common electrode voltage output node and the source voltage output node.

Abstract: The liquid crystal display device of the present invention includes a first substrate, a second substrate, and a vertical alignment type liquid crystal layer provided between the first substrate and the second substrate, and includes a plurality of picture element regions each defined by a first electrode provided on one side of the first substrate that is closer to the liquid crystal layer and a second electrode provided on the second substrate so as to oppose the first electrode via the liquid crystal layer. The first substrate includes a first orientation-regulating structure in each of the plurality of picture element regions, the first orientation-regulating structure exerting an orientation-regulating force so as to form a plurality of liquid crystal domains in the liquid crystal layer, each of the liquid crystal domains taking a radially-inclined orientation in the presence of an applied voltage.

Abstract: The liquid crystal display device of the present invention includes a first substrate, a second substrate, and a vertical alignment type liquid crystal layer provided between the first substrate and the second substrate, and includes a plurality of picture element regions each defined by a first electrode provided on one side of the first substrate that is closer to the liquid crystal layer and a second electrode provided on the second substrate so as to oppose the first electrode via the liquid crystal layer. The first substrate includes a first orientation-regulating structure in each of the plurality of picture element regions, the first orientation-regulating structure exerting an orientation-regulating force so as to form a plurality of liquid crystal domains in the liquid crystal layer, each of the liquid crystal domains taking a radially-inclined orientation in the presence of an applied voltage.

Abstract: The liquid crystal display device of this invention includes a plurality of picture element regions each defined by a first electrode provided on a face of a first substrate facing a liquid crystal layer and a second electrode provided on a second substrate so as to oppose the first electrode via the liquid crystal layer sandwiched therebetween. In each of the picture element regions, the first electrode has a plurality of openings and a solid portion, the liquid crystal layer is in a vertical orientation state when no voltage is applied between the first electrode and the second electrode, and when a voltage is applied between the first electrode and the second electrode, a plurality of liquid crystal domains each in a radially-inclined orientation state are respectively formed in the plurality of openings and the solid portion by inclined electrode fields generated at respective edge portions of the openings of the first electrode.