Abstract: An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects VSSL for supplying a first power supply voltage VSS to memory cells MC are formed in a metal interconnect layer in which a plurality of wordlines WL are formed; and wherein a plurality of second power supply interconnects VDDL for supplying a second power supply voltage VDD to the memory cells are formed in another metal interconnect layer in which a plurality of bitlines BL are formed, the second power supply voltage VDD being higher than the first power supply voltage VSS. A plurality of bitline protection interconnects SHD are formed in a layer above the bitlines BL, and each of the bitline protection interconnects SHD at least partially covers one of the bitlines BL in a plan view.

Abstract: An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TC1 and TC2, each of the control transistors being provided corresponding to each output line of the data driver block and controlled. by using a common control signal, and a pad arrangement region in which data driver pads P1 and P2 for electrically connecting the data lines and the output lines QL1 and QL2 of the data driver block are disposed. The control transistors TC1 and TC2 are disposed in the pad arrangement region.

Abstract: In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.

Abstract: An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects for supplying a first power supply voltage to a plurality of memory cells are provided in a metal interconnect layer in which a plurality of bitlines are formed; wherein a second power supply interconnect for supplying a second power supply voltage to the memory cells is provided in a metal interconnect layer in which a plurality of wordlines are formed, the second power supply voltage being higher than the first power supply voltage; wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is provided in a layer above the bitline protection interconnects, the third power supply voltage being

Abstract: An integrated circuit device includes a data driver block DB, a memory block MB, and a logic circuit block LB. The data driver block DB includes a data driver DR and a buffer circuit BF which buffers a driver control signal from the logic circuit block LB and outputs the buffered driver control signal to the data driver DR. The memory block MB includes a memory cell array MA and a row address decoder RD which selects a wordline. The data driver block DB and the memory block MB are disposed along a direction D1, the buffer circuit BF and the data driver DR are disposed along a direction D2, the row address decoder RD and the memory cell array MA are disposed along the direction D2, and the buffer circuit BF and the row address decoder RD are disposed along the direction D1.

Abstract: An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.

Abstract: Each of RAM blocks provided in a display memory and disposed along a first direction in which bitlines extend includes a sense amplifier circuit which outputs M-bit data upon one wordline selection (M is an integer larger than 1). At least M memory cells are arranged in each of the RAM blocks along a second direction in which wordlines extend. M sense amplifier cells to which M-bit data read from the M memory cells is input are provided in the sense amplifier circuit. L sense amplifier cells of the M sense amplifier cells are disposed at a position corresponding to L memory cells adjacent in the second direction (L is an integer which satisfies 2?L<M/2). When the height of the memory cell in the second direction is denoted by MCY and the height of the sense amplifier cell in the second direction is denoted by SACY, “(L?1)×MCY<SACY?L×MCY” is satisfied.

Abstract: An integrated circuit device, including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a scan driver block SB, a power supply circuit block PB, a data driver block DB, and a memory block MB. The scan driver block SB and the power supply circuit block PB are disposed adjacent to each other along the direction D1; and the data driver block DB and the memory block MB are disposed adjacent to each other along the direction D1.

Abstract: An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a high-speed interface circuit block HB which transfers data through a serial bus using differential signals, and a circuit block other than HB. The high-speed interface circuit block HB is disposed as an Mth circuit block CBM (2?M?N?1) of the circuit blocks CB1 to CBN.

Abstract: An integrated circuit device includes a driver macrocell in which a plurality of circuit blocks are integrated into a macrocell. The driver macrocell includes a data driver block DB for driving data lines, a memory block MB which stores image data, and a pad block PDB in which pads for electrically connecting output lines of the data driver block DB with the data lines are disposed. The data driver block DB and the memory block MB are disposed along a direction D1, and the pad block PDB is disposed on the D2 side of the data driver block DB and the memory block MB.

Abstract: An integrated circuit device, including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines; and the memory block MB includes a memory cell array, a row address decoder RD, and a sense amplifier block SAB.

Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.

Abstract: An integrated circuit device includes a scan driver block SB which generates a control signal for driving a scan line, a pad PDt electrically connected with the scan line, and transistors pDTrt and nDTrt of which a connection node DNDt is electrically connected with the PDt pad and which are push-pull connected between a high-potential-side power supply and a low-potential-side power supply. The transistors pDTrt and nDTrt are gate-controlled based on the control signal from the scan driver block SB. The pad PDt is disposed in an upper layer of at least one of the transistors pDTrt and nDTrt so that the pad PDt overlaps part or the entirety of at least one of the transistors pDTrt and nDTrt.

Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1 when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is a direction D1 and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is a direction D2. At least one of the circuit blocks on both ends of the circuit blocks CB1 to CBN is a scan driver block for driving a scan line. Or, the scan driver block SB is disposed along the direction D1 on the side of the first to Nth circuit blocks in the direction D2.

Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines. The memory block MB and the data driver block DB are disposed adjacent to each other along the first direction D1.

Abstract: An integrated circuit device includes: first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The first to Nth circuit blocks CB1 to CBN includes a logic circuit block LB which sets grayscale characteristic adjustment data; and a grayscale voltage generation circuit block GB which generates grayscale voltages based on the set adjustment data. The logic circuit block LB and the grayscale voltage generation circuit block GB are disposed adjacent to each other along the direction D1.

Abstract: An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.

Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1, a first interface region provided on the D2 side of the circuit blocks CB1 to CBN, and a second interface region provided on the D4 side of the circuit blocks CB1 to CBN. The circuit blocks CB1 to CBN include a data driver block DB and a circuit block other than the data driver block DB. When the widths of the first interface region, the circuit blocks CB1 to CBN, and the second interface region in the direction D2 are respectively W1, WB, and W2, the integrated circuit device has a width W in the direction D2 of “W1+WB+W2?W<W1+2×WB+W2”.

Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a logic circuit block LB, a grayscale voltage generation circuit block GB, data driver blocks DB1 to DB4, and a power supply circuit block PB. The data driver blocks DB1 to DB4 are disposed between the logic circuit block LB and the grayscale voltage generation circuit block GB, and the power supply circuit block PB.