Abstract: The multiplication circuit is formed in such a manner that the intermediate sums of partial products are divided into a lower places group and a higher places group and the operations for obtaining the products of the lower places group alone of the intermediate sums already found are carried out parallel to the processing for obtaining the higher places group of the intermediate sums to obtain the higher products thereafter, noting to the fact that the intermediate sums of partial products are found sequentially from lower places to higher places. By adopting such an arrangement, the operations for obtaining the higher places group of the intermediate sums can be processed in parallel with the operations for obtaining the products of the lower places group of the intermediate sums already found, and the higher products are found thereafter. Therefore, the time required for the former-stage processing and that required for the latter-stage processing can be made more uniform.

Abstract: A data scan test circuit includes first through fourth latch circuits (L10 through L40). Data are latched in the third latch circuit (L40). A scan register consisting of the first, second and fourth latch circuits (L10, L20, L30) which become necessary when circuit blocks (CB1, CB2) are tested is made effective. Thus, unnecessary scan registers are put in the "through" state, thereby substantially reducing the number or scan paths in scan operation, and shortening the test time.

Abstract: A semiconductor apparatus including a semiconductor integrated circuit is disclosed. The semiconductor integrated circuit includes a circuit block, a plurality of boundary scan registers, a system data terminal, a test signal terminal and a control circuit. The control circuit responds to a test signal to generate control signals (a select signal LT, shift clock signals SCLK1 and SCLK2, a capture clock signal CPCLK and an update clock signal UPCLK) for controlling the boundary scan registers. The boundary scan registers are connected in cascade to each other and each connected to the circuit block. Each boundary scan register includes a selector circuit (12) and latch circuits (13, 14, 15). The latch circuit (13) responds to the shift clock signal SCLK1 to shift data of an adjacent preceding boundary scan register, an also responds to the update clock signal UPCLK to capture data from the selector circuit (12). The selector circuit (12) responds to the select signal LT to select system data or test data.

Abstract: A parallel multiplier utilizing arrays of logic cells. A first circuit logic array forms and sums partial products of the most significant bits of the multiplicand with the multiplier. A second logic array forms and sums partial products of the least significant bits of the multiplier. A third circuit logic array which adds results of the partial product addition performed in parallel by the first and second circuit logic arrays. Since the first and second logic groups execute, respectively, the partial product addition in parallel, the number of adding steps is reduced as a whole and the operation speed is improved. The third logic array is disposed between the first and second logic arrays, resulting in a reasonable structure for circuit integrations and further improving system speed.

Abstract: In a circuit for testing integrated circuit devices, scan registers (8.about.16) and data selecting circuits (20-28) are connected between a plurality of circuit blocks (29.about.31) in correspondence with the number of bits of the data, with the scan registers connected to each other by a shift register path so as to have a function of one shift register as a whole. A register selecting circuit (20.about.28) is connected to a clock input terminal (T1, T2) of the scan register. The scan registers other than those corresponding to the logic circuit block to be tested are selected by the register selecting circuit. Consequently, clocks for scanning scan registers other than those provided before and after the required circuit block are eliminated, enabling reduction of time required for scan test.

Abstract: An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).

Abstract: A programmable logic array comprises an OR circuit (67) and an AND circuit (68). A voltage lower than a power-supply voltage is applied to product term lines (57-60) from a power supply portion (69) in response to conduction of p channel transistors (31-34) by a clock signal to be precharged, and a voltage lower than the power-supply voltage is applied to output lines (54, 55) from a power supply portion (70) in response to conduction of p channel transistors (39, 40) by the clock signal. Therefore, applied voltages of the product term lines and the output lines are lowered, so that responsibility of circuit is improved, whereby a programmable logic array with a high speed operation is obtained.

Abstract: A semiconductor integrated circuit includes cascaded asynchronous sequential logic circuits. Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data. Additional gating circuitry is provided between the scanning shift registers and the inputs of the asynchronous sequential circuits to prevent new data latched into the scanning shift register from causing the asynchronous sequential circuit connected to the scanning shift register output from changing state during testing. This same additional circuitry may be used to provide pulses of controlled width and/or timing to asynchronous sequential circuit inputs in response to externally generated gating control signals.

Abstract: A semiconductor integrated circuit device for transmitting data between a plurality of circuit blocks at least one thereof including a sequential circuit and enabling the circuit blocks to test in a scan testing type which has a plurality of scan registers provided between the plurality of circuit blocks corresponding to the number of bits of data to be transmitted for outputting the output data of the previous stage circuit block as it is at ordinary operating time and for holding and outputting the output data of the previous circuit block or test data for scan test synchronously with an external clock at testing time so that the circuits are connected by a shift register pass in such a manner that the entirety has one shaft register function, and a latch circuit provided at its data input terminal to the data output terminal of the corresponding scan register for outputtting the output data of the corresponding scan register as it is to the circuit block of next stage at ordinary operation time and holding

Abstract: A test circuit of a semiconductor integrated circuit apparatus comprising a latch circuit connected to an output terminal of a scan register for holding output data of the scan register stored before scanning in a scan mode during the test operation.

Abstract: A semiconductor integrated circuit device includes a plurality of latch circuits which are provided between adjacent circuit blocks. Each latch circuit functions to transfer output data from a preceding circuit block directly to a subsequent circuit block during a normal operation of the circuit device, to hold the output data until a scanning of associated scan register and supply them to the subsequent circuit block in a scan mode of a test operation and to hole the output data while outputting them in synchronism with an external clock in a test mode of the test operation.

Abstract: A semiconductor memory device includes: a memory cell constituted by MOSFETs; a bit line for transmitting a writing and a reading information to or from the memory cell therethrough; a writing-in control signal line for controlling the writing operation onto the memory cell; a first conductive type MOSFET with a source thereof being connected to a power supply terminal, with a gate thereof being connected to the writing-in control signal line, and with a drain thereof being connected to the bit line; the first conductive type MOSFET being adapted to charge up the bit line when no writing is performed in the memory cell; a second conductive type MOSFET with first control line thereof being connected to the bit line, with a gate thereof being connected to the writing-in control signal line, and with a second control line thereof being connected to the output terminal of the writing circuit; and the second conductive type MOSFET being adapted to transmit to the bit line an output from the writing circuit.

Abstract: A semiconductor memory device, which comprises: a memory cell constituted by MOSFETs; a bit line for transmitting a writing and a reading information to the memory cell therethrough; a writing-in control signal line for controlling the writing operation onto the memory cell; and a writing circuit for transmitting the writing information input from the outside to the bit line at the time of writing but raising the voltage of the bit line up to a power supply voltage at the time of non-writing.