Abstract: Proposed is a technique for providing assistance so that an image is captured with the intended composition. An image processing device according to the present invention includes a correction means capable of carrying out image blur correction, and can output an image generated on the basis of a cut-out region which has been cut out from an image based on imaging performed by an imaging device. The image processing device includes a control means for controlling notification related to a range from which the cut-out region can be cut out while the image blur correction performed by the correction means is activated.

Abstract: A timing window (TW) representing a time zone where a signal transition possibly occurs in a time axis is generated for each of input signals in input terminals in a multi-input logic cell based on a signal transition timing in each of the input terminals. An overlap between the timing windows (TW) of input signals is detected, and a circuit delay time is calculated by selectively using one of a synchronous transition time and an asynchronous transition time in accordance with the overlap between the timing windows (TW). These processing steps are sequentially repeated to eliminate an optimistic or pessimistic analysis in the calculation of delay times in the multi-input logic cell.

Abstract: A data communication apparatus is provided with an image reader which reads a document image, a storage which stores image data of the document image read by the image reader and registers one or a plurality of transmitting destinations, a data communication unit having a plurality of communication lines, and a communication control unit which controls a transmission start timing of the image data to the transmitting destinations. The communication control unit controls the data communication unit to start transmitting the image data to a first transmitting destination at a timing when reading of the document image by the image reader starts, when a plurality of transmitting destinations are registered.

Abstract: In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.

Abstract: Reverse bias voltage VM is applied to any one of self light emitting elements arranged on a light emitting panel 1 under detection mode. Current corresponding to weak current flowing to the element is supplied to a transistor Q3 by the operation of a current mirror circuit comprised of transistors Q1, Q2. The current mirror circuit is formed with the transistor Q3 as a control side current source transistor and transistors Q4 to Q7 as a controlled side current source transistor. The sizes of the controlled side current source transistors Q4 to Q7 are set to, for example, 1:2:4:8 with respect to the control side current source transistor Q3 so as to construct current amplifying means. Current value amplified by a current comparison type comparator 7 is compared with current value from a reference current source 8 and its output is latched by a latch circuit 9 and stored in a data register 10.

Abstract: An image forming device having a communication unit includes a system control unit which controls the entire image forming apparatus, the system control unit having a CPU that is set in one of a normal mode, a power-saving mode and a sleep mode by controlling a power supply unit. A real-time clock keeps track of hours, minutes and seconds of a current time and outputs a signal indicating the current time. A register stores a return time that indicates a time the CPU is to be switched from one of the power-saving mode and the sleep mode to the normal mode. A comparator compares the current time of the clock with the return time of the register, and outputs, when a match occurs, a control signal to the CPU so that the CPU is switched to the normal mode.

Abstract: In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.

Abstract: In a method of analyzing a power noise based on the circuit information of a semiconductor integrated circuit device, the power noise is analyzed in consideration of the influence of the impedance of a substrate. Consequently, the impedance of the substrate which has not been conventionally considered is taken into consideration. Thus, precision in the analysis can be enhanced more greatly.

Abstract: A method for designing a semiconductor integrated circuit is provided that is capable of a timing simulation that is approximate to an actual operation by reducing the effect of IR drop on the timing without reducing an effective area necessary for arrangement of elements or the number of pads that can be used other than power supply pads and without increasing the processing time. In a FF driving ability change procedure, a flip-flop having a delay time larger than a transition time from a state in which an IR drop occurs in a power supply voltage to a state of an ideal power supply voltage is substituted for an arbitrary flip-flop. Thus, a delay library considering IR drop may be produced previously only for the flop-flop, thus enabling a production time of the library to be reduced and improving the calculation accuracy of the delay time in the delay calculation procedure. Furthermore, the substitution of a flip-flop having a low driving ability enables the area to be reduced.

Abstract: A delay calculation method considering a net adjacent to a delay calculation object net of a semiconductor integrated circuit includes: an adjacent net internal resistance selecting step of selecting a combination of static state of an adjacent net driving cell; a coupling capacitance grounding step of multiplying a coupling capacitance by a coefficient obtained from an internal resistance of the adjacent net driving cell selected by the adjacent net internal resistance selecting step, and the like, and grounding the value obtained thereby as the coupling capacitance of the delay calculating object net; and a delay value deriving step of deriving the delay value from a circuit obtained by these steps. A problem of the delay calculation method that an accurate delay value cannot be obtained because in actuality, the adjacent wire whose potential fluctuates is approximated to zero potential is solved by this structure.

Abstract: Reverse bias voltage VM is applied to any one of self light emitting elements arranged on a light emitting panel 1 under detection mode. Current corresponding to weak current flowing to the element is supplied to a transistor Q3 by the operation of a current mirror circuit comprised of transistors Q1, Q2. The current mirror circuit is formed with the transistor Q3 as a control side current source transistor and transistors Q4 to Q7 as a controlled side current source transistor. The sizes of the controlled side current source transistors Q4 to Q7 are set to, for example, 1:2:4:8 with respect to the control side current source transistor Q3 so as to construct current amplifying means. Current value amplified by a current comparison type comparator 7 is compared with current value from a reference current source 8 and its output is latched by a latch circuit 9 and stored in a data register 10.

Abstract: An image forming device having a communication unit includes a system control unit which controls the entire image forming apparatus, the system control unit having a CPU that is set in one of a normal mode, a power-saving mode and a sleep mode by controlling a power supply unit. A real-time clock keeps track of hours, minutes and seconds of a current time and outputs a signal indicating the current time. A register stores a return time that indicates a time the CPU is to be switched from one of the power-saving mode and the sleep mode to the normal mode. A comparator compares the current time of the clock with the return time of the register, and outputs, when a match occurs, a control signal to the CPU so that the CPU is switched to the normal mode.

Abstract: Provided is a self light emitting display module by which defect can be reported to a user immediately in a case where defect occurs for example in a pixel of a light emitting display panel. Output terminal potentials of constant current sources I1-In which supply constant currents to respective EL elements E11-Enm arranged in a light emitting display panel 1 are drawn via inspection lines TL1-TLn and are selected by a select switch SW1. A selected electrical potential is supplied to first and second comparators CP1, CP2 whose comparison reference potentials differ, and their comparison results are latched by latch circuits LC1, LC2 respectively to be stored in a data register 6 provided as a memory means. A determination is made as to whether or not defect has occurred in a portion of a part including the respective EL elements and respective drivers 2,3 through data stored in the data register 6.

Abstract: A method for designing a semiconductor integrated circuit device for connecting between terminals of transistors formed on a silicon wafer by metal wiring. The method includes a first step of carrying out a schematic arrangement so as to minimize a distance of a wiring for connecting between the transistors or wiring capacitance based on input information on transistors; a second step of producing information on a voltage drop value based on the schematic arrangement of the transistors; and a third step of arranging the transistors based on the information on a voltage drop value.

Abstract: An image forming device having a communication unit includes a system control unit which controls the entire image forming apparatus, the system control unit having a CPU that is set in one of a normal mode, a power-saving mode and a sleep mode by controlling a power supply unit. A real-time clock keeps track of hours, minutes and seconds of a current time and outputs a signal indicating the current time. A register stores a return time that indicates a time the CPU is to be switched from one of the power-saving mode and the sleep mode to the normal mode. A comparator compares the current time of the clock with the return time of the register, and outputs, when a match occurs, a control signal to the CPU so that the CPU is switched to the normal mode.

Abstract: A self-light-emitting display module by which a defect can be quickly notified to a user, for example, when the defect is caused in a pixel on a display panel is provided. A routine for verifying whether a defect is caused on a signal line including a pixel on the display panel, and the like is executed when, for example, operating power is supplied to the self-light-emitting display module; or on a regular basis under a state in which the operating power is supplied; or when ON-operation of a detecting switch is executed by a user; and the like. A circuit for generating a reverse bias voltage is used as a current source. A defect state of a pixel, signal lines including the pixels and the like is recognized by a wave form of a current when the current is applied to an EL element in a non-light-emitting direction. When a defect is detected, a defect notification unit is operated.

Abstract: A system for detecting reverse rotation of a 4-cycle, internal combustion engine with three or more cylinder for an outboard motor mounted on a boat, whose output is connected to a propeller such that the boat is propelled forward or reverse. In the system, it is determined whether a counted value of crank angle signals generated once every 30 crank angles is a multiple of a predetermined number (e.g., four in six cylinders), when the cylinders are identified and it is determined that engine rotates reverse when the counted value is determined to be not the multiple and the engine is immediately stopped. With this, it becomes possible to accurately detect the reverse rotation of the engine and prevent its further reverse rotation.

Abstract: A system for detecting malfunction of an equipment such as an alternator or a hydraulic switch that is connected to an internal combustion engine and generates an output. In the system, it is discriminated periodically for a predetermined period of time whether the output of the equipment is within a predetermined range, a number of times that the output of the equipment is discriminated to be out of the predetermined range is counted; and the equipment is determined to have malfunctioned when the count is equal to or greater than the reference value. With this, it becomes possible to detect the malfunction of the equipment accurately.

Abstract: Where there are wirings with different film thicknesses or a sheet resistance in a non-scraped state of a wiring layer cannot be obtained as a result of the CPM technique, a wiring resistance according to a film thickness when an LSI is manufactured is acquired by automatic processing to reduce its difference from a real resistance, and accurate voltage drop analysis is carried out to reduce malfunction in a real chip. In a semiconductor circuit device with a plurality of kinds of film thicknesses in the same wiring layer, with a variation occurring in the wiring film thickness when wirings are formed on a silicon wafer, or a warp occurring in an upper layer because the stacking of lower layers is not uniform in the manufacturing process of the wiring, an error of the wiring resistance due to the difference in the film thickness or warp of the wiring is corrected to produce a virtual layout data.

Abstract: A method for designing a semiconductor integrated circuit is provided that is capable of a timing simulation that is approximate to an actual operation by reducing the effect of IR drop on the timing without reducing an effective area necessary for arrangement of elements or the number of pads that can be used other than power supply pads and without increasing the processing time. In a FF driving ability change procedure, a flip-flop having a delay time larger than a transition time from a state in which an IR drop occurs in a power supply voltage to a state of an ideal power supply voltage is substituted for an arbitrary flip-flop. Thus, a delay library considering IR drop may be produced previously only for the flop-flop, thus enabling a production time of the library to be reduced and improving the calculation accuracy of the delay time in the delay calculation procedure. Furthermore, the substitution of a flip-flop having a low driving ability enables the area to be reduced.