Abstract: The semiconductor device that supplies a charging current to a bootstrap capacitor includes a semiconductor layer, an N+-type diffusion region, an N-type diffusion region, a P+-type diffusion region, a P-type diffusion region, an N+-type diffusion region, a source electrode, a drain electrode, a back gate electrode, and a gate electrode. The N+-type diffusion region and the N-type diffusion region are electrically connected to a first electrode of the bootstrap capacitor. The N+-type diffusion region is supplied with a power supply voltage. The source electrode is connected to the N+-type diffusion region and is supplied with the power supply voltage. The back gate electrode is connected to a region separated from the N+-type diffusion region and is grounded. The breakdown voltage between the source electrode and the back gate electrode is greater than the power supply voltage.

Abstract: A polyamic acid manufacturing system for manufacturing a polyamic acid is disclosed using, as raw materials, a first solution in which a polyaddition-type first polymerizable compound is dissolved and a second solution in which a polyaddition-type second polymerizable compound that reacts with the first polymerizable compound through polyaddition is dissolved. The polyamic acid manufacturing system may include: a first supply part for supplying the first solution; a second supply part for supplying the second solution; a first combining part; and a first reaction part, thereby producing a first polymerization solution in which the polyamic acid is dissolved. Further, the polyamic acid manufacturing system may include: a first supply step of supplying the first solution; a second supply step of supplying the second solution; a first combining step; and a first reaction step, thereby producing a first polymerization solution in which the polyamic acid is dissolved.

Abstract: A semiconductor device includes a well region, a buffer region, an insulating film, an electrode, and an electric field relaxing structure. An impurity concentration in the buffer region is reduced in a direction away from the active region. An end portion of the electrode is located at a position closer to the active region than an end portion of the buffer region. The electric field relaxing structure includes a plurality of RESURF layers each surrounding the buffer region in a plan view and formed in a surface layer of the semiconductor substrate.

Abstract: An annular valve in which the shape of a sealing surface of a valve body is optimized thus suppressing the occurrence of pressure loss in gas on the periphery of the sealing surface and extending the service life of the annular valve.

Abstract: A semiconductor device includes a well region, a buffer region, an insulating film, an electrode, and an electric field relaxing structure. An impurity concentration in the buffer region is reduced in a direction away from the active region. An end portion of the electrode is located at a position closer to the active region than an end portion of the buffer region. The electric field relaxing structure includes a plurality of RESURF layers each surrounding the buffer region in a plan view and formed in a surface layer of the semiconductor substrate.

Abstract: A three-dimensional shaping apparatus includes a shaping table 31, a squeegee 32, a sintering device, a cutting device, transport pathways 4 through which metal powder and fumes that have been discharged to the outer side of a shaping tank 1 after cutting with the cutting device, and metal powder that has been discharged to the outer side of a chamber 2 surrounding the shaping tank 1 without forming part of the laminated layer, are transported to a sifter 5 located at the top of a powder tank 6, and supply devices for inert gas that does not react with the metal powder at an inlet 40 of each transport pathway 4, so as to suppress oxidation of metal powder in the transport pathway for collected metal powder and fumes, and also dust explosion due to sudden oxidation of the same.

Abstract: A three-dimensional shaping apparatus includes a shaping table 31, a squeegee 32, a sintering device, a cutting device, transport pathways 4 through which metal powder and fumes that have been discharged to the outer side of a shaping tank 1 after cutting with the cutting device, and metal powder that has been discharged to the outer side of a chamber 2 surrounding the shaping tank 1 without forming part of the laminated layer, are transported to a sifter 5 located at the top of a powder tank 6, and supply devices for inert gas that does not react with the metal powder at an inlet 40 of each transport pathway 4, so as to suppress oxidation of metal powder in the transport pathway for collected metal powder and fumes, and also dust explosion due to sudden oxidation of the same.

Abstract: The solar cell module includes an anti-glare film on a transparent insulating substrate. The anti-glare film is a continuous film that contains transparent inorganic fine particles in an inorganic binder, and is free of cracks. The anti-glare film preferably has an average thickness d1 of 500 nm to 2000 nm, and a maximum surface height Ry1 of 1000 nm to 10000 nm. The inorganic binder is preferably composed mainly of silicon oxide containing Si—O bonds obtained by the hydrolysis of Si—H bonds and Si—N bonds. The inorganic fine particles are non-spherical particles having ground surfaces, and preferably have an average primary particle size, calculated from cross-sectional observations of the anti-glare film, of 0.1 ?m to 5.0 ?m.

Abstract: A measurement device according to one aspect of the present invention includes a first controller configured to output a control signal and a second controller configured to perform a first control and then to perform a second control based on the control signal output from the first controller. The control signal designates both an input signal and a calibration signal to be converted into a digital input signal and a digital calibration signal, respectively. The input signal is input from an outside of the measurement device. The calibration signal is previously prepared. The first control is for selecting the input signal and converting the selected input signal into the digital input signal.

Abstract: An anti-glare film includes a first inorganic layer and a second inorganic layer in this order has form a substrate side. The first inorganic layer contains transparent spherical inorganic fine particles in an inorganic binder. The inorganic binder in the first inorganic layer mainly includes a silicon oxide containing Si—O bonds obtained by hydrolysis of a Si—H bond and a Si—N bond. The second inorganic layer contains an inorganic binder. Preferably, an average thickness of the first inorganic layer is 500 to 2000 nm, an average thickness of the second inorganic layer is 50 to 1000 nm, and a ratio is 0.025 to 0.5. The second inorganic layer may furthermore contain fine particles. The anti-glare film can be used as an anti-glare film for a solar cell module.

Abstract: An analog front-end circuit for measurement used as an interface between a sensor and a control device includes: an isolated part including at least an AD conversion circuit configured to serve as an interface to the sensor; a non-isolated part including at least a control circuit configured to serve as an interface to the control device; and an isolated communication unit configured to perform isolated half-duplex communication between the isolated part and the non-isolated part. The control circuit is configured to transmit an AD conversion instruction to the AD conversion circuit after providing setting for measurement to the isolated part via the isolated communication unit, obtain a result of AD conversion by the AD conversion circuit from the isolated part via the isolated communication unit, and transfer the obtained AD conversion result to the control device.

Abstract: A measurement device according to one aspect of the present invention includes a first controller configured to output a control signal and a second controller configured to perform a first control and then to perform a second control based on the control signal output from the first controller. The control signal designates both an input signal and a calibration signal to be converted into a digital input signal and a digital calibration signal, respectively. The input signal is input from an outside of the measurement device. The calibration signal is previously prepared. The first control is for selecting the input signal and converting the selected input signal into the digital input signal.

Abstract: The solar cell module includes an anti-glare film on a transparent insulating substrate. The anti-glare film is a continuous film that contains transparent inorganic fine particles in an inorganic binder, and is free of cracks. The anti-glare film preferably has an average thickness d1 of 500 nm to 2000 nm, and a maximum surface height Ry1 of 1000 nm to 10000 nm. The inorganic binder is preferably composed mainly of silicon oxide containing Si—O bonds obtained by the hydrolysis of Si—H bonds and Si—N bonds. The inorganic fine particles are non-spherical particles having ground surfaces, and preferably have an average primary particle size, calculated from cross-sectional observations of the anti-glare film, of 0.1 ?m to 5.0 ?m.

Abstract: A first isolation trench insulates and separates a low-voltage region, a high-voltage region, and a connection region of the semiconductor layer from each other. A low-potential signal processing circuit is in the low-voltage region, and operates at a lower potential. A high-potential signal processing circuit is in the high-voltage region, and operates at a higher potential. A capacitor is on the connection region and transmits the second alternating current signal from the low-potential signal processing circuit to the high-potential signal processing circuit. The capacitor includes a low-potential electrode connected to the low-potential signal processing circuit, and a high-potential electrode connected to the high-potential signal processing circuit. First wiring layers of the low-potential electrode and second wiring layers of the high-potential electrode are capacitively coupled. Side wall surfaces of the first wiring layers and those of the second wiring layers are opposed to each other.

Abstract: A first isolation trench insulates and separates a low-voltage region, a high-voltage region, and a connection region of the semiconductor layer from each other. A low-potential signal processing circuit is in the low-voltage region, and operates at a lower potential. A high-potential signal processing circuit is in the high-voltage region, and operates at a higher potential. A capacitor is on the connection region and transmits the second alternating current signal from the low-potential signal processing circuit to the high-potential signal processing circuit. The capacitor includes a low-potential electrode connected to the low-potential signal processing circuit, and a high-potential electrode connected to the high-potential signal processing circuit. First wiring layers of the low-potential electrode and second wiring layers of the high-potential electrode are capacitively coupled. Side wall surfaces of the first wiring layers and those of the second wiring layers are opposed to each other.

Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.

Abstract: An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern.

Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.

Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.

Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.