Patents by Inventor Kazuhiro Shimomura

Kazuhiro Shimomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230017911
    Abstract: The invention relates to compositions and methods of treating a sleep-wake disorder or neurodegenerative diseases using modified resistant maltodextrin.
    Type: Application
    Filed: May 31, 2022
    Publication date: January 19, 2023
    Inventors: Kazuhiro Shimomura, Martha Hotz Vitaterna, Phyllis C. Zee
  • Patent number: 11344569
    Abstract: The invention relates to compositions and methods of treating a sleep-wake disorder or neurodegenerative diseases using modified resistant maltodextrin.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: May 31, 2022
    Assignee: Northwestern University
    Inventors: Kazuhiro Shimomura, Martha Hotz Vitaterna, Phyllis C. Zee
  • Publication number: 20210353587
    Abstract: A composition includes at least one of a modified glucal or galactal molecule. The molecules are useful for the treatment of cancer, particularly in a human patient, more particularly in a human patient exhibiting cell-specific increases in glucose uptake without a corresponding lactate production. The compounds are also useful for treating a human that has hypoxic cells expressing elevated levels of HIT activity, a plurality of cells displaying a lower amplitude of circadian oscillation or an increase in reactive oxygen species in mitochondria of the cells of the human.
    Type: Application
    Filed: November 11, 2019
    Publication date: November 18, 2021
    Inventors: Akihito TAIRA, Kazuhiro SHIMOMURA
  • Publication number: 20190151348
    Abstract: The invention relates to compositions and methods of treating a sleep-wake disorder or neurodegenerative diseases using modified resistant maltodextrin.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 23, 2019
    Inventors: Kazuhiro Shimomura, Martha Hotz Vitaterna, Phyllis C. Zee
  • Patent number: 9496861
    Abstract: A multiplexer for voltage measurement includes: a first switch disposed on a first channel extending between at least one high-voltage input terminal and an output terminal; a plurality of second switches respectively disposed on second channels each extending between each of input terminals other than the high-voltage input terminal and the output terminal; and a third switch disposed between a group of the plurality of second switches and an output terminal side end of the first switch. Each of the first switch and the third switch is configured to operate even by a voltage higher than a power supply voltage.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: November 15, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuhiro Shimomura, Ryouta Akeyama
  • Patent number: 9217778
    Abstract: A signal processor includes: a plurality of first capacitors provided for respective output terminals of a plurality of multiplexers, the first capacitors having their one ends connected to the respective output terminals of the multiplexers, the first capacitors being charged in accordance with voltages outputted from the respective output terminals; a differential amplifier including an input terminal connected to the other ends of the first capacitors; a second capacitor connected between the input terminal and an output terminal of the differential amplifier; and a second switch connected parallel to the second capacitor. First switches included in at least one of the plurality of multiplexers are configured as high-voltage switches that allow operation at a voltage higher than an operating voltage of first switches included in the other multiplexer or multiplexers.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: December 22, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Kazuhiro Shimomura
  • Publication number: 20140117975
    Abstract: A multiplexer for voltage measurement includes: a first switch disposed on a first channel extending between at least one high-voltage input terminal and an output terminal; a plurality of second switches respectively disposed on second channels each extending between each of input terminals other than the high-voltage input terminal and the output terminal; and a third switch disposed between a group of the plurality of second switches and an output terminal side end of the first switch. Each of the first switch and the third switch is configured to operate even by a voltage higher than a power supply voltage.
    Type: Application
    Filed: December 23, 2013
    Publication date: May 1, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Kazuhiro SHIMOMURA, Ryouta AKEYAMA
  • Publication number: 20140111217
    Abstract: A signal processor includes: a plurality of first capacitors provided for respective output terminals of a plurality of multiplexers, the first capacitors having their one ends connected to the respective output terminals of the multiplexers, the first capacitors being charged in accordance with voltages outputted from the respective output terminals; a differential amplifier including an input terminal connected to the other ends of the first capacitors; a second capacitor connected between the input terminal and an output terminal of the differential amplifier; and a second switch connected parallel to the second capacitor. First switches included in at least one of the plurality of multiplexers are configured as high-voltage switches that allow operation at a voltage higher than an operating voltage of first switches included in the other multiplexer or multiplexers.
    Type: Application
    Filed: December 27, 2013
    Publication date: April 24, 2014
    Applicant: PANASONIC CORPORATION
    Inventor: Kazuhiro SHIMOMURA
  • Publication number: 20100092009
    Abstract: An amplification circuit amplifies an input signal. A signal detecting circuit detects whether the input signal is in a signal present state or in a signal absent state. A period detecting circuit detects a signal present duration for which the signal detecting circuit detects that the input signal is in the signal present state. A time setting circuit sets a control waiting time, depending on the signal present duration detected by the period detecting circuit. A control circuit limits outputting of the amplification circuit after the control waiting time set by the time setting circuit has elapsed since the signal detecting circuit detected the signal absent state of the input signal.
    Type: Application
    Filed: June 3, 2009
    Publication date: April 15, 2010
    Inventor: Kazuhiro SHIMOMURA
  • Patent number: 7579893
    Abstract: An NchMOS transistor (1) is provided for muting of an output terminal (10) to which positive and negative output signals are outputted, and a mute switch circuit (3) is provided for controlling on/off of the transistor (1) by switching a voltage applied to the gate of the transistor (1). When muting is turned off, the back gate of the transistor (1) is biased by resistance division between resistors (R1 and R2) connected in series between the output terminal (10) and a predetermined negative potential (VSS).
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: August 25, 2009
    Assignee: Panasonic Corporation
    Inventors: Kazuhiro Shimomura, Makoto Yamamoto
  • Publication number: 20080314507
    Abstract: It is an object of the invention to provide a method for producing an IC chip capable of producing an IC chip with a thickness as extremely thin as 50 ?m or thinner, for example, about 25 to 30 ?m at a high productivity.
    Type: Application
    Filed: August 2, 2004
    Publication date: December 25, 2008
    Inventors: Munehiro Hatai, Satoshi Hayashi, Masateru Fukuoka, Shigeru Danjo, Yasuhiko Oyama, Kazuhiro Shimomura, Daihei Sugita, Yoshikazu Kitajima
  • Publication number: 20080211565
    Abstract: AnNchMOS transistor (1) is provided for muting of an output terminal (10) to which positive and negative output signals are outputted, and a mute switch circuit (3) is provided for controlling on/off of the transistor (1) by switching a voltage applied to the gate of the transistor (1). When muting is turned off, the back gate of the transistor (1) is biased by resistance division between resistors (R1 and R2) connected in series between the output terminal (10) and a predetermined negative potential (VSS).
    Type: Application
    Filed: April 8, 2008
    Publication date: September 4, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiro Shimomura, Makoto Yamamoto
  • Patent number: 7372325
    Abstract: An NchMOS transistor (1) is provided for muting of an output terminal (10) to which positive and negative output signals are outputted, and a mute switch circuit (3) is provided for controlling on/off of the transistor (1) by switching a voltage applied to the gate of the transistor (1). When muting is turned off, the back gate of the transistor (1) is biased by resistance division between resistors (R1 and R2) connected in series between the output terminal (10) and a predetermined negative potential (VSS).
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: May 13, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiro Shimomura, Makoto Yamamoto
  • Publication number: 20070076903
    Abstract: An NchMOS transistor (1) is provided for muting of an output terminal (10) to which positive and negative output signals are outputted, and a mute switch circuit (3) is provided for controlling on/off of the transistor (1) by switching a voltage applied to the gate of the transistor (1). When muting is turned off, the back gate of the transistor (1) is biased by resistance division between resistors (R1 and R2) connected in series between the output terminal (10) and a predetermined negative potential (VSS).
    Type: Application
    Filed: July 25, 2006
    Publication date: April 5, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiro Shimomura, Makoto Yamamoto
  • Publication number: 20070037364
    Abstract: It is the object of the invention to provide a method for manufacturing a semiconductor chip capable of obtaining a semiconductor chip at a high manufacturing efficiency without damages. The invention is a method for manufacturing a semiconductor chip, which comprises a tape adhesion step of sticking a pressure sensitive adhesive tape for dicing having a pressure sensitive adhesive layer containing a gas generating agent for generating a gas by radiating light to a semiconductor wafer with a circuit formed; a dicing step for dicing the wafer with the pressure sensitive adhesive tape for dicing stuck and dividing the semiconductor wafer into each semiconductor chip; a separation step of separating at least a portion of the pressure sensitive adhesive tape for dicing from the semiconductor chip by radiating light to the divided each semiconductor chip; and a pickup step of picking the semiconductor chip up by a needle-less pickup method.
    Type: Application
    Filed: December 2, 2004
    Publication date: February 15, 2007
    Inventors: Daihei Sugita, Masateru Fukuoka, Munehiro Hatai, Satoshi Hayashi, Kazuhiro Shimomura, Yoshikazu Kitajima, Yasuhiko Oyama
  • Publication number: 20060269715
    Abstract: An object of the present invention is to provide an adhesive substance capable of being easily peeled off without damaging an adherend by giving stimulation thereto, a tape employing this adhesive substance, and a method for peeling off the adhesive substance. An adhesive substance, which contains a gas-generating agent for generating gas by stimulation, gas generated from said gas-generating agent being discharged to the outside of said adhesive substance so as not to foam said adhesive substance, and gas generated from said gas-generating agent peeling at least part of an adhesive surface of said adhesive substance off an adherend so as to decrease adhesive strength.
    Type: Application
    Filed: July 24, 2006
    Publication date: November 30, 2006
    Inventors: Munehiro Hatai, Masateru Fukuoka, Satoshi Hayashi, Shigeru Danjo, Yasuhiko Oyama, Kazuhiro Shimomura, Tsuyoshi Hasegawa
  • Publication number: 20050173051
    Abstract: An object of the present invention is to provide an adhesive substance capable of being easily peeled off without damaging an adherend by giving stimulation thereto, a tape employing this adhesive substance, and a method for peeling off the adhesive substance. An adhesive substance, which contains a gas-generating agent for generating gas by stimulation, gas generated from said gas-generating agent being discharged to the outside of said adhesive substance so as not to foam said adhesive substance, and gas generated from said gas-generating agent peeling at least part of an adhesive surface of said adhesive substance off an adherend so as to decrease adhesive strength.
    Type: Application
    Filed: June 3, 2002
    Publication date: August 11, 2005
    Inventors: Munehiro Hatai, Masateru Fukuoka, Satoshi Hayashi, Shigeru Danjo, Yasuhiko Oyama, Kazuhiro Shimomura, Tsuyoshi Hasegawa
  • Patent number: 6866739
    Abstract: In a film with metal foil of the present invention, a metal foil is stuck to the surface of a resin film via an adhesive layer. The adhesive is formed by crosslinking an acrylic polymer obtained by the copolymerization of a (meth)acrylic acid ester with a carboxyl group-containing radically polymerizable monomer, with a polyfunctional compound having a functional group reactive with the carboxyl group. The film with metal foil is very useful for producing a multi-layer wiring board by the so-called transfer method. By using this film, there can be produced a multi-layer wiring board having a fine and highly dense wiring/circuit layer and having a very excellently flat surface.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: March 15, 2005
    Assignees: Kyocera Corporation, Sekisui Chemical Corporation
    Inventors: Akihiko Nishimoto, Katsura Hayashi, Yasuhiko Ohyama, Shigeru Danjo, Kazuhiro Shimomura
  • Publication number: 20040261943
    Abstract: An object of the present invention is to provide an adhesive substance capable of being easily peeled off without using light and damaging an adherend, a method for peeling off the adhesive substance, and a connected structure.
    Type: Application
    Filed: August 18, 2004
    Publication date: December 30, 2004
    Inventors: Masateru Fukuoka, Munehiro Hatai, Yasuhiko Oyama, Shigeru Danjo, Satoshi Hayashi, Kazuhiro Shimomura, Tsuyoshi Hasegawa
  • Publication number: 20040248382
    Abstract: The purpose of the invention is to provide a double-sided adhesive tape which prevents a wafer from damaging even when the wafer has a considerably thin thickness of about 50 &mgr;m, which has improved handlability, which is favorably used for processing of an IC chip and which facilitates its peeling, and a method for manufacturing an IC chip using it.
    Type: Application
    Filed: June 23, 2004
    Publication date: December 9, 2004
    Inventors: Munehiro Hatai, Masateru Fukuoka, Satoshi Hayashi, Shigeru Danjo, Yasuhiko Oyama, Kazuhiro Shimomura, Tsuyoshi Hasegawa