Patents by Inventor Kazuhiro Tashiro
Kazuhiro Tashiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11072236Abstract: A fuel supply device includes an inlet pipe, a first end of the inlet pipe configured to be connected to an oil supply port and a second end of the inlet pipe configured to be connected to a fuel tank and an air flow path, an upstream side end of the air flow path configured to be open to the outside and a downstream side end of the air flow path configured to be connected to the fuel tank. The air flow path includes a negative pressure valve configured to move a valve body to open a valve port when the pressure in the fuel tank becomes a negative pressure and an air filter disposed upstream of the negative pressure valve.Type: GrantFiled: October 30, 2018Date of Patent: July 27, 2021Assignee: Toyota Jidosha Kabushiki KaishaInventors: Takanori Sakai, Shinji Shimokawa, Toshikazu Ito, Kazuhiro Tashiro
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Patent number: 10882393Abstract: A fuel supply device includes a valve body and a filter unit accommodating an air filter and a valve cap are attached to a tubular portion provided on a side surface of an inlet pipe. When a fuel tank has a negative pressure, the valve body opens and the negative pressure is eliminated by clean atmospheric air introduction. A projection portion is provided on the filter unit side of the valve body. Accordingly, attachment of the valve body into the tubular portion and attachment of the tubular portion and the filter unit are reliably performed, the reliability of valve body opening and closing is improved, and attachment workability is improved.Type: GrantFiled: March 8, 2019Date of Patent: January 5, 2021Assignee: Toyota Jidosha Kabushiki KaishaInventors: Koji Kojima, Takanori Sakai, Yoshihiro Ito, Kazuhiro Tashiro, Shinji Shimokawa
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Publication number: 20190275881Abstract: A fuel supply device includes a valve body and a filter unit accommodating an air filter and a valve cap are attached to a tubular portion provided on a side surface of an inlet pipe. When a fuel tank has a negative pressure, the valve body opens and the negative pressure is eliminated by clean atmospheric air introduction. A projection portion is provided on the filter unit side of the valve body. Accordingly, attachment of the valve body into the tubular portion and attachment of the tubular portion and the filter unit are reliably performed, the reliability of valve body opening and closing is improved, and attachment workability is improved.Type: ApplicationFiled: March 8, 2019Publication date: September 12, 2019Applicant: Toyota Jidosha Kabushiki KaishaInventors: Koji Kojima, Takanori Sakai, Yoshihiro Ito, Kazuhiro Tashiro, Shinji Shimokawa
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Publication number: 20190152314Abstract: A fuel supply device includes an inlet pipe, a first end of the inlet pipe configured to be connected to an oil supply port and a second end of the inlet pipe configured to be connected to a fuel tank and an air flow path, an upstream side end of the air flow path configured to be open to the outside and a downstream side end of the air flow path configured to be connected to the fuel tank. The air flow path includes a negative pressure valve configured to move a valve body to open a valve port when the pressure in the fuel tank becomes a negative pressure and an air filter disposed upstream of the negative pressure valve.Type: ApplicationFiled: October 30, 2018Publication date: May 23, 2019Applicant: Toyota Jidosha Kabushiki KaishaInventors: Takanori Sakai, Shinji Shimokawa, Toshikazu Ito, Kazuhiro Tashiro
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Patent number: 8797055Abstract: A prober includes a probe card provided with a support board and a probe attached to the support board, a stage on which a measurement wafer is mounted, a camera provided over the probe card to observe an electrode pad of a first semiconductor chip formed on the measurement wafer, and a stage moving unit for moving the position of the stage relative to the probe card.Type: GrantFiled: June 24, 2011Date of Patent: August 5, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Kazuhiro Tashiro
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Patent number: 8759119Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.Type: GrantFiled: February 26, 2013Date of Patent: June 24, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Shigeyuki Maruyama, Yasuyuki Itoh, Tetsurou Honda, Kazuhiro Tashiro, Makoto Haseyama, Kenichi Nagashige, Yoshiyuki Yoneda, Hirohisa Matsuki
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Patent number: 8671557Abstract: A tray is provided in combination with an electronic component attaching tool attached to the tray and includes an attachment depression part that includes an inner wall and to which an electronic component is attached, wherein forming of the inner wall of the attachment depression part does not substantially depend on an external shape of the electronic component, and a standard part formed in the inner wall of the attachment depression part and engaging with a first structure part of the electronic component attaching tool to align a position of the electronic component attaching tool to the standard part when a position of the electronic component is aligned to a first position of the tray using the electronic component attaching tool, the standard part having a shape which does not substantially depend on the external shape of the electronic component.Type: GrantFiled: September 23, 2011Date of Patent: March 18, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Daisuke Koizumi, Shigeyuki Maruyama, Kazuhiro Tashiro, Naoyuki Watanabe
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Patent number: 8404496Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.Type: GrantFiled: May 24, 2006Date of Patent: March 26, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Shigeyuki Maruyama, Yasuyuki Itoh, Tetsurou Honda, Kazuhiro Tashiro, Makoto Haseyama, Kenichi Nagashige, Yoshiyuki Yoneda, Hirohisa Matsuki
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Patent number: 8268670Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.Type: GrantFiled: September 22, 2011Date of Patent: September 18, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama
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Patent number: 8164181Abstract: A semiconductor device packaging structure is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.Type: GrantFiled: August 31, 2010Date of Patent: April 24, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama
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Patent number: 8159250Abstract: A testing device of a semiconductor device includes a first board having a plurality of openings; a frame body provided in the openings, the frame body having a frame in which a plurality of probe needles is provided; and a plurality of second boards provided perpendicular to the first board in the periphery of the openings, the second boards being connected to the first board; wherein the probe needles pierce the frame so as to be connected to the second boards from the periphery of the frame body via the openings.Type: GrantFiled: July 10, 2009Date of Patent: April 17, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Yuji Maruyama, Kazuhiro Tashiro, Kazuhiko Shimabayashi, Shigeru Goto, Takayuki Nakashiro, Susumu Koshinuma, Masayoshi Shirakawa
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Publication number: 20120005883Abstract: An electronic component attaching tool suitable for an external shape of a semiconductor device is prepared. The electronic component attaching tool has a function of aligning a position of the semiconductor device to an IC socket. The electronic component attaching tool is mounted on the standard surface that is formed on the IC socket substantially regardless of the external shape of the semiconductor device. The semiconductor device is then aligned and attached to the IC socket by using the electronic component attaching tool, and the electronic component attaching tool is removed from the IC socket. Another electronic component attaching tool suitable for an external shape of another semiconductor device is prepared, and the same procedure as the above is performed to align and attach this semiconductor device to the same type IC socket.Type: ApplicationFiled: September 23, 2011Publication date: January 12, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Daisuke Koizumi, Shigeyuki Maruyama, Kazuhiro Tashiro, Naoyuki Watanabe
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Publication number: 20120005875Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.Type: ApplicationFiled: September 22, 2011Publication date: January 12, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama
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Patent number: 8051554Abstract: An IC socket in which an electronic component is attached to a predetermined position of the IC socket, the IC socket including a fixed part including a contact pin which is connected to a terminal of the electronic component when a position of the electronic component is aligned to the predetermined position of the IC socket using an electronic component attaching tool, the contact pin including a pair of end portions on an upper surface of the fixed part; a movable part that is movable to the fixed part when the movable part is pushed down to apply a force to the contact pin of the fixed part so as to separate the pair of end portions of the contact pin from each other; and a standard part that is formed on the movable part and engages with the electronic component attaching tool to align a position of the electronic component attaching tool to the standard part when a position of the electronic component is aligned to the predetermined position of the IC socket using the electronic attaching tool, the stanType: GrantFiled: April 16, 2008Date of Patent: November 8, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Daisuke Koizumi, Shigeyuki Maruyama, Kazuhiro Tashiro, Naoyuki Watanabe
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Publication number: 20110254574Abstract: A prober includes a probe card provided with a support board and a probe attached to the support board, a stage on which a measurement wafer is mounted, a camera provided over the probe card to observe an electrode pad of a first semiconductor chip formed on the measurement wafer, and a stage moving unit for moving the position of the stage relative to the probe card.Type: ApplicationFiled: June 24, 2011Publication date: October 20, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Kazuhiro Tashiro
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Patent number: 7915720Abstract: The present invention provides a high-quality semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective element in case the other is determined defective; moreover, only the defective unit is exchangeable with a non-defective unit. The semiconductor integrated circuit device of the present invention contains multiple semiconductor integrated circuit elements, e.g. semiconductor integrated circuit devices 14 and 16, and a circuit board 12 which relays the respective semiconductor integrated circuit elements 14 and 16, and at least a part of the circuit board 12, e.g.Type: GrantFiled: April 27, 2006Date of Patent: March 29, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Kazuhiro Tashiro, Hitoshi Izuru
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Publication number: 20110049699Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.Type: ApplicationFiled: August 31, 2010Publication date: March 3, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama
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Patent number: 7825676Abstract: A contact terminal formed of an electrically conductive material is arranged in each of a plurality of holed of a contactor substrate. An electrically conductive part is formed on an inner surface of each hole. The contact terminal has a first contact part that contacts a terminal of an electronic part and a second contact part that contacts the electrically conductive part in a middle portion. When the contact terminal bends by the first contact part being pressed, the second contact part contacts the electrically conductive part of the contactor substrate and an appropriate degree of contact pressure is obtained.Type: GrantFiled: May 10, 2007Date of Patent: November 2, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Daisuke Koizumi, Naohito Kohashi, Kazuhiro Tashiro, Takumi Kumatabara
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Patent number: 7807481Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.Type: GrantFiled: April 24, 2008Date of Patent: October 5, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama
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Publication number: 20090267630Abstract: A testing device of a semiconductor device includes a first board having a plurality of openings; a frame body provided in the openings, the frame body having a frame in which a plurality of probe needles is provided; and a plurality of second boards provided perpendicular to the first board in the periphery of the openings, the second boards being connected to the first board; wherein the probe needles pierce the frame so as to be connected to the second boards from the periphery of the frame body via the openings.Type: ApplicationFiled: July 10, 2009Publication date: October 29, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Yuji Maruyama, Kazuhiro Tashiro, Kazuhiko Shimabayashi, Shigeru Goto, Takayuki Nakashiro, Susumu Koshinuma, Masayoshi Shirakawa