Patents by Inventor Kazuhiro Tashiro

Kazuhiro Tashiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11945923
    Abstract: Disclosed is a method for producing an electrolytic capacitor, the method including the steps of preparing an anode foil that includes a dielectric layer, a cathode foil, and a fiber structure; preparing a conductive polymer dispersion liquid that contains a conductive polymer component and a dispersion medium; producing a separator by applying the conductive polymer dispersion liquid to the fiber structure and then removing at least a portion of the dispersion medium; and producing a capacitor element by sequentially stacking the anode foil, the separator, and the cathode foil. The dispersion medium contains water. The fiber structure contains a synthetic fiber in an amount of 50 mass % or more. The fiber structure has a density of 0.2 g/cm3 or more and less than 0.45 g/cm3.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: April 2, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Daisuke Kubo, Hiroyuki Arima, Tomoyuki Tashiro, Kazuhiro Takatani, Kenta Chashiro, Shumpei Matsushita
  • Patent number: 11072236
    Abstract: A fuel supply device includes an inlet pipe, a first end of the inlet pipe configured to be connected to an oil supply port and a second end of the inlet pipe configured to be connected to a fuel tank and an air flow path, an upstream side end of the air flow path configured to be open to the outside and a downstream side end of the air flow path configured to be connected to the fuel tank. The air flow path includes a negative pressure valve configured to move a valve body to open a valve port when the pressure in the fuel tank becomes a negative pressure and an air filter disposed upstream of the negative pressure valve.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 27, 2021
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Takanori Sakai, Shinji Shimokawa, Toshikazu Ito, Kazuhiro Tashiro
  • Patent number: 10882393
    Abstract: A fuel supply device includes a valve body and a filter unit accommodating an air filter and a valve cap are attached to a tubular portion provided on a side surface of an inlet pipe. When a fuel tank has a negative pressure, the valve body opens and the negative pressure is eliminated by clean atmospheric air introduction. A projection portion is provided on the filter unit side of the valve body. Accordingly, attachment of the valve body into the tubular portion and attachment of the tubular portion and the filter unit are reliably performed, the reliability of valve body opening and closing is improved, and attachment workability is improved.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: January 5, 2021
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Koji Kojima, Takanori Sakai, Yoshihiro Ito, Kazuhiro Tashiro, Shinji Shimokawa
  • Publication number: 20190275881
    Abstract: A fuel supply device includes a valve body and a filter unit accommodating an air filter and a valve cap are attached to a tubular portion provided on a side surface of an inlet pipe. When a fuel tank has a negative pressure, the valve body opens and the negative pressure is eliminated by clean atmospheric air introduction. A projection portion is provided on the filter unit side of the valve body. Accordingly, attachment of the valve body into the tubular portion and attachment of the tubular portion and the filter unit are reliably performed, the reliability of valve body opening and closing is improved, and attachment workability is improved.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 12, 2019
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventors: Koji Kojima, Takanori Sakai, Yoshihiro Ito, Kazuhiro Tashiro, Shinji Shimokawa
  • Publication number: 20190152314
    Abstract: A fuel supply device includes an inlet pipe, a first end of the inlet pipe configured to be connected to an oil supply port and a second end of the inlet pipe configured to be connected to a fuel tank and an air flow path, an upstream side end of the air flow path configured to be open to the outside and a downstream side end of the air flow path configured to be connected to the fuel tank. The air flow path includes a negative pressure valve configured to move a valve body to open a valve port when the pressure in the fuel tank becomes a negative pressure and an air filter disposed upstream of the negative pressure valve.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 23, 2019
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventors: Takanori Sakai, Shinji Shimokawa, Toshikazu Ito, Kazuhiro Tashiro
  • Patent number: 8797055
    Abstract: A prober includes a probe card provided with a support board and a probe attached to the support board, a stage on which a measurement wafer is mounted, a camera provided over the probe card to observe an electrode pad of a first semiconductor chip formed on the measurement wafer, and a stage moving unit for moving the position of the stage relative to the probe card.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: August 5, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kazuhiro Tashiro
  • Patent number: 8759119
    Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: June 24, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shigeyuki Maruyama, Yasuyuki Itoh, Tetsurou Honda, Kazuhiro Tashiro, Makoto Haseyama, Kenichi Nagashige, Yoshiyuki Yoneda, Hirohisa Matsuki
  • Patent number: 8671557
    Abstract: A tray is provided in combination with an electronic component attaching tool attached to the tray and includes an attachment depression part that includes an inner wall and to which an electronic component is attached, wherein forming of the inner wall of the attachment depression part does not substantially depend on an external shape of the electronic component, and a standard part formed in the inner wall of the attachment depression part and engaging with a first structure part of the electronic component attaching tool to align a position of the electronic component attaching tool to the standard part when a position of the electronic component is aligned to a first position of the tray using the electronic component attaching tool, the standard part having a shape which does not substantially depend on the external shape of the electronic component.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Daisuke Koizumi, Shigeyuki Maruyama, Kazuhiro Tashiro, Naoyuki Watanabe
  • Patent number: 8404496
    Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: March 26, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shigeyuki Maruyama, Yasuyuki Itoh, Tetsurou Honda, Kazuhiro Tashiro, Makoto Haseyama, Kenichi Nagashige, Yoshiyuki Yoneda, Hirohisa Matsuki
  • Patent number: 8268670
    Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: September 18, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama
  • Patent number: 8164181
    Abstract: A semiconductor device packaging structure is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: April 24, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama
  • Patent number: 8159250
    Abstract: A testing device of a semiconductor device includes a first board having a plurality of openings; a frame body provided in the openings, the frame body having a frame in which a plurality of probe needles is provided; and a plurality of second boards provided perpendicular to the first board in the periphery of the openings, the second boards being connected to the first board; wherein the probe needles pierce the frame so as to be connected to the second boards from the periphery of the frame body via the openings.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: April 17, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yuji Maruyama, Kazuhiro Tashiro, Kazuhiko Shimabayashi, Shigeru Goto, Takayuki Nakashiro, Susumu Koshinuma, Masayoshi Shirakawa
  • Publication number: 20120005883
    Abstract: An electronic component attaching tool suitable for an external shape of a semiconductor device is prepared. The electronic component attaching tool has a function of aligning a position of the semiconductor device to an IC socket. The electronic component attaching tool is mounted on the standard surface that is formed on the IC socket substantially regardless of the external shape of the semiconductor device. The semiconductor device is then aligned and attached to the IC socket by using the electronic component attaching tool, and the electronic component attaching tool is removed from the IC socket. Another electronic component attaching tool suitable for an external shape of another semiconductor device is prepared, and the same procedure as the above is performed to align and attach this semiconductor device to the same type IC socket.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 12, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Daisuke Koizumi, Shigeyuki Maruyama, Kazuhiro Tashiro, Naoyuki Watanabe
  • Publication number: 20120005875
    Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.
    Type: Application
    Filed: September 22, 2011
    Publication date: January 12, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama
  • Patent number: 8051554
    Abstract: An IC socket in which an electronic component is attached to a predetermined position of the IC socket, the IC socket including a fixed part including a contact pin which is connected to a terminal of the electronic component when a position of the electronic component is aligned to the predetermined position of the IC socket using an electronic component attaching tool, the contact pin including a pair of end portions on an upper surface of the fixed part; a movable part that is movable to the fixed part when the movable part is pushed down to apply a force to the contact pin of the fixed part so as to separate the pair of end portions of the contact pin from each other; and a standard part that is formed on the movable part and engages with the electronic component attaching tool to align a position of the electronic component attaching tool to the standard part when a position of the electronic component is aligned to the predetermined position of the IC socket using the electronic attaching tool, the stan
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: November 8, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Daisuke Koizumi, Shigeyuki Maruyama, Kazuhiro Tashiro, Naoyuki Watanabe
  • Publication number: 20110254574
    Abstract: A prober includes a probe card provided with a support board and a probe attached to the support board, a stage on which a measurement wafer is mounted, a camera provided over the probe card to observe an electrode pad of a first semiconductor chip formed on the measurement wafer, and a stage moving unit for moving the position of the stage relative to the probe card.
    Type: Application
    Filed: June 24, 2011
    Publication date: October 20, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Kazuhiro Tashiro
  • Patent number: 7915720
    Abstract: The present invention provides a high-quality semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective element in case the other is determined defective; moreover, only the defective unit is exchangeable with a non-defective unit. The semiconductor integrated circuit device of the present invention contains multiple semiconductor integrated circuit elements, e.g. semiconductor integrated circuit devices 14 and 16, and a circuit board 12 which relays the respective semiconductor integrated circuit elements 14 and 16, and at least a part of the circuit board 12, e.g.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: March 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazuhiro Tashiro, Hitoshi Izuru
  • Publication number: 20110049699
    Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 3, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama
  • Patent number: 7825676
    Abstract: A contact terminal formed of an electrically conductive material is arranged in each of a plurality of holed of a contactor substrate. An electrically conductive part is formed on an inner surface of each hole. The contact terminal has a first contact part that contacts a terminal of an electronic part and a second contact part that contacts the electrically conductive part in a middle portion. When the contact terminal bends by the first contact part being pressed, the second contact part contacts the electrically conductive part of the contactor substrate and an appropriate degree of contact pressure is obtained.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: November 2, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Daisuke Koizumi, Naohito Kohashi, Kazuhiro Tashiro, Takumi Kumatabara
  • Patent number: 7807481
    Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: October 5, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama