Patents by Inventor Kazuhiro Tashiro

Kazuhiro Tashiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7145250
    Abstract: An LSI package comprises an LSI element and a wiring board. The plurality of pin terminals of the LSI element each includes a first conductive layer and a second conductive layer superposed on the first conductive layer. The plurality of pin terminals of the wiring board each includes a third conductive layer joined to the second conductive layer, and the wiring board further comprises outer joining terminals. The first, second, and third conductive layers are made of materials causing the metallic bond between the second conductive layer and third conductive layer to be stronger than the metallic bond between the first conductive layer and second conductive layer. The LSI element is tested using the outer joining terminals of the wiring board. The second conductive layer and third conductive layer are joined to attain a metallic bond through aggregation derived from pressure, and are reliably brought into electrical contact with each other for a test.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: December 5, 2006
    Assignee: Fujitsu Limited
    Inventors: Shigeyuki Maruyama, Toru Nishino, Kazuhiro Tashiro
  • Patent number: 7129726
    Abstract: A testing device can perform a test on an arbitrary one of a plurality of semiconductor devices by pressing the semiconductor devices onto a contactor from a back side of the semiconductor device. A test circuit board has a contactor provided with contact pieces corresponding to external connection terminals of semiconductor devices to be tested. A support board is capable of mounting the semiconductor devices thereon in an aligned state. A stage supports the support board. A press head presses the semiconductor devices to be tested mounted on the support board so as to cause external connection terminals of the semiconductor devices to be tested to contact with the contact pieces of the contactor. The stage is movable to a position at which at least one of the semiconductor devices to be tested, which are mounted on the support board, faces the contactor.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: October 31, 2006
    Assignee: Fujitsu Limited
    Inventors: Kazuhiro Tashiro, Yasuyuki Itou, Shigeyuki Maruyama, Yoshikazu Arisaka
  • Publication number: 20060220667
    Abstract: A testing device can perform a test on an arbitrary one of a plurality of semiconductor devices by pressing the semiconductor devices onto a contactor from a back side of the semiconductor device. A test circuit board has a contactor provided with contact pieces corresponding to external connection terminals of semiconductor devices to be tested. A support board is capable of mounting the semiconductor devices thereon in an aligned state. A stage supports the support board. A press head presses the semiconductor devices to be tested mounted on the support board so as to cause external connection terminals of the semiconductor devices to be tested to contact with the contact pieces of the contactor. The stage is movable to a position at which at least one of the semiconductor devices to be tested, which are mounted on the support board, faces the contactor.
    Type: Application
    Filed: August 25, 2005
    Publication date: October 5, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Kazuhiro Tashiro, Yasuyuki Itou, Shigeyuki Maruyama, Yoshikazu Arisaka
  • Patent number: 7112889
    Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: September 26, 2006
    Assignee: Fujitsu Limited
    Inventors: Shigeyuki Maruyama, Yasuyuki Itoh, Tetsurou Honda, Kazuhiro Tashiro, Makoto Haseyama, Kenichi Nagashige, Yoshiyuki Yoneda, Hirohisa Matsuki
  • Publication number: 20060097356
    Abstract: A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line.
    Type: Application
    Filed: February 23, 2005
    Publication date: May 11, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Shigeru Fujii, Yoshikazu Arisaka, Hitoshi Izuru, Kazuhiro Tashiro, Shigeyuki Maruyama
  • Publication number: 20060061379
    Abstract: A burn-in testing method to perform tests with a semiconductor device operated in an atmosphere at a prescribed temperature characterized in that operation instruction signals instructing an operation of the semiconductor device are repeatedly supplied while supplying power to the semiconductor device, and increases and decreases in a power supply current corresponding to the operation instruction signals are counted.
    Type: Application
    Filed: March 14, 2005
    Publication date: March 23, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Hitoshi Izuru, Kazuhiro Tashiro
  • Publication number: 20050204551
    Abstract: An electronic component attaching tool suitable for an external shape of a semiconductor device is prepared. The electronic component attaching tool has a function of aligning a position of the semiconductor device to an IC socket. The electronic component attaching tool is mounted on the standard surface that is formed on the IC socket substantially regardless of the external shape of the semiconductor device. The semiconductor device is then aligned and attached to the IC socket by using the electronic component attaching tool, and the electronic component attaching tool is removed from the IC socket. Another electronic component attaching tool suitable for an external shape of another semiconductor device is prepared, and the same procedure as the above is performed to align and attach this semiconductor device to the same type IC socket.
    Type: Application
    Filed: May 11, 2005
    Publication date: September 22, 2005
    Applicant: Fujitsu Limited
    Inventors: Daisuke Koizumi, Shigeyuki Maruyama, Kazuhiro Tashiro, Naoyuki Watanabe
  • Publication number: 20050189649
    Abstract: An LSI package comprises an LSI element and a wiring board. The plurality of pin terminals of the LSI element each includes a first conductive layer and a second conductive layer superposed on the first conductive layer. The plurality of pin terminals of the wiring board each includes a third conductive layer joined to the second conductive layer, and the wiring board further comprises outer joining terminals. The first, second, and third conductive layers are made of materials causing the metallic bond between the second conductive layer and third conductive layer to be stronger than the metallic bond between the first conductive layer and second conductive layer. The LSI element is tested using the outer joining terminals of the wiring board. The second conductive layer and third conductive layer are joined to attain a metallic bond through aggregation derived from pressure, and are reliably brought into electrical contact with each other for a test.
    Type: Application
    Filed: April 25, 2005
    Publication date: September 1, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Shigeyuki Maruyama, Toru Nishino, Kazuhiro Tashiro
  • Patent number: 6927343
    Abstract: A contactor has a film substrate of an insulating material and plural wiring patterns on the substrate. A first end of each wiring pattern extends out from a first edge of the substrate as a first contact terminal and a second end of each wiring pattern extends out from a second edge of the substrate as a second contact terminal, and a part of the contactor located between the first end and second end can be deformed resiliently.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: August 9, 2005
    Assignee: Fujitsu Limited
    Inventors: Naoyuki Watanabe, Shigeyuki Maruyama, Kazuhiro Tashiro, Daisuke Koizumi, Takafumi Hashitani
  • Patent number: 6924174
    Abstract: An electronic component attaching tool suitable for an external shape of a semiconductor device is prepared. The electronic component attaching tool has a function of aligning a position of the semiconductor device to an IC socket. The electronic component attaching tool is mounted on the standard surface that is formed on the IC socket substantially regardless of the external shape of the semiconductor device. The semiconductor device is then aligned and attached to the IC socket by using the electronic component attaching tool, and the electronic component attaching tool is removed from the IC socket. Another electronic component attaching tool suitable for an external shape of another semiconductor device is prepared, and the same procedure as the above is performed to align and attach this semiconductor device to the same type IC socket.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: August 2, 2005
    Assignee: Fujitsu Limited
    Inventors: Daisuke Koizumi, Shigeyuki Maruyama, Kazuhiro Tashiro, Naoyuki Watanabe
  • Publication number: 20050162180
    Abstract: A semiconductor testing device is used for testing a semiconductor device which has at least one spherical connection terminal. The testing device includes an insulating substrate having an opening formed therein at a position corresponding to the position of the spherical connection terminal, and a contact member, formed on the insulating substrate, including a connection portion which is connected with the spherical connection terminal, at least the connection portion being deformable and extending into the opening.
    Type: Application
    Filed: February 1, 2005
    Publication date: July 28, 2005
    Applicant: FIJITSU LIMITED
    Inventors: Shigeyuki Maruyama, Kazuhiro Tashiro, Makoto Haseyama, Futoshi Fukaya
  • Patent number: 6882169
    Abstract: A semiconductor testing device is used for testing a semiconductor device which has at least one spherical connection terminal. The testing device includes an insulating substrate having an opening formed there in at a position corresponding to the position of the spherical connection terminal, and a contact member, formed on the insulating substrate, including a connection portion which is connected with the spherical connection terminal, at least the connection portion being deformable and extending into the opening.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: April 19, 2005
    Assignee: Fujitsu Limited
    Inventors: Shigeyuki Maruyama, Kazuhiro Tashiro, Makoto Haseyama
  • Publication number: 20050072972
    Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.
    Type: Application
    Filed: March 16, 2004
    Publication date: April 7, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama
  • Publication number: 20040266272
    Abstract: A contactor has contact electrodes elastically deformable in a direction of thickness of the contactor so that the contactor can make a contact with a semiconductor device with an appropriate contact pressure. The contactor is positioned between the semiconductor device and a test board so as to electrically connect the semiconductor device to the test board. Each of a plurality of contact electrodes has a first contact electrode part, a second contact electrode part and a connecting part electrically connecting the first contact electrode part to the second contact electrode part. The first contact electrode part contacts an electrode of the semiconductor device. The second contact electrode part contacts a terminal of the test board. A combining member has an insulating characteristic and holds the connecting part of each of the contact electrodes in a predetermined arrangement.
    Type: Application
    Filed: July 28, 2004
    Publication date: December 30, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Shigeyuki Maruyama, Kazuhiro Tashiro, Naoyuki Watanabe, Daisuke Koizumi, Takafumi Hashitani, Ei Yano
  • Publication number: 20040239357
    Abstract: A contactor configured to be electrically connected to the terminals of an electronic component is disclosed. The connector includes multiple contact electrodes contacting the terminals of the electronic component and multiple elastic electrodes each composed of an electrically conductive elastic body. The elastic electrodes generate a pressing force for pressing the contact electrodes against the terminals of the electronic component. The contact electrodes are separable from the elastic electrodes.
    Type: Application
    Filed: May 27, 2004
    Publication date: December 2, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Kazuhiro Tashiro, Shigeyuki Maruyama, Daisuke Koizumi, Takumi Kumatabara, Keisuke Fukuda
  • Patent number: 6791345
    Abstract: A contactor has contact electrodes elastically deformable in a direction of thickness of the contactor so that the contactor can make a contact with a semiconductor device with an appropriate contact pressure. The contactor is positioned between the semiconductor device and a test board so as to electrically connect the semiconductor device to the test board. Each of a plurality of contact electrodes has a first contact electrode part, a second contact electrode part and a connecting part electrically connecting the first contact electrode part to the second contact electrode part. The first contact electrode part contacts an electrode of the semiconductor device. The second contact electrode part contacts a terminal of the test board. A combining member has an insulating characteristic and holds the connecting part of each of the contact electrodes in a predetermined arrangement.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: September 14, 2004
    Assignee: Fujitsu Limited
    Inventors: Shigeyuki Maruyama, Kazuhiro Tashiro, Naoyuki Watanabe, Daisuke Koizumi, Takafumi Hashitani, Ei Yano
  • Patent number: 6767219
    Abstract: A contactor has a contactor substrate and a plurality of contact electrodes formed on the contactor substrate. Each contact electrode is formed by a metal wire bent between one end joined to the contactor substrate and the other end. An inclined plane is formed by a cutting surface. A fracture surface formed by a tension fracture is formed at the apex portion of the contact electrode.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: July 27, 2004
    Assignee: Fujitsu Limited
    Inventors: Shigeyuki Maruyama, Naoyuki Watanabe, Kazuhiro Tashiro, Naohito Kohashi, Osamu Igawa, Tetsuya Fujisawa
  • Publication number: 20040124866
    Abstract: A semiconductor testing device is used for testing a semiconductor device which has at least one spherical connection terminal. The testing device includes an insulating substrate having an opening formed therein at a position corresponding to the position of the spherical connection terminal, and a contact member, formed on the insulating substrate, including a connection portion which is connected with the spherical connection terminal, at least the connection portion being deformable and extending into the opening.
    Type: Application
    Filed: October 16, 2003
    Publication date: July 1, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Shigeyuki Maruyama, Kazuhiro Tashiro, Makoto Haseyama, Futoshi Fukaya
  • Publication number: 20040077969
    Abstract: An apparatus has a first electrode group (1) including at least one electrode and arranged on the abdominal surface of a subject (human) with the navel of the subject serving as a reference position, a second electrode group (2) including at least one electrode and arranged on the back surface of the subject, a third electrode group (3) including at least two electrodes and arranged on the surface of the subject at an intermediate position between the first and second electrode groups (1, 2), and a controller (8) to supply a current between an electrode selected from the first electrode group (1) and an electrode selected from the second electrode group (2), measure a voltage generated between two electrodes of the third electrode group (3), and compute an abdominal fat quantity of the subject according to the measured voltage.
    Type: Application
    Filed: August 22, 2003
    Publication date: April 22, 2004
    Inventors: Tomohiro Onda, Mitsuhiro Katashima, Junichi Nojima, Susumu Fujinami, Kazuhiro Tashiro
  • Publication number: 20040055150
    Abstract: An electronic component attaching tool suitable for an external shape of a semiconductor device is prepared. The electronic component attaching tool has a function of aligning a position of the semiconductor device to an IC socket. The electronic component attaching tool is mounted on the standard surface that is formed on the IC socket substantially regardless of the external shape of the semiconductor device. The semiconductor device is then aligned and attached to the IC socket by using the electronic component attaching tool, and the electronic component attaching tool is removed from the IC socket. Another electronic component attaching tool suitable for an external shape of another semiconductor device is prepared, and the same procedure as the above is performed to align and attach this semiconductor device to the same type IC socket.
    Type: Application
    Filed: September 5, 2003
    Publication date: March 25, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Daisuke Koizumi, Shigeyuki Maruyama, Kazuhiro Tashiro, Naoyuki Watanabe