Patents by Inventor Kazuhiro Yamashita

Kazuhiro Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5590137
    Abstract: A semiconductor IC tester is capable of undertaking a double-speed test for a IC device under test wherein the test pattern application and resulted signal comparison are performed both in the first half and the latter half of a test cycle of the IC tester without sacrificing the number of test pins. In the double-speed mode, the generating speed of test patterns is doubled as follows. In the first half of the test cycle, a flip-flop is set or reset at the timings of the outputs of first and second delay circuits, respectively. Moreover, in the latter half of test cycle, the flip-flop is set or reset at the timings of the output of third and fourth delay circuits, respectively, which are used usually as enabling and disabling a driver which generates a final form of test signal to the device under test.
    Type: Grant
    Filed: October 13, 1994
    Date of Patent: December 31, 1996
    Assignee: Advantest Corporation
    Inventor: Kazuhiro Yamashita
  • Patent number: 5518579
    Abstract: An acid solution is fed onto a TiN film formed on a semiconductor substrate. So, the TiN film is dipped into the acid solution, whereupon the surface of the semiconductor substrate is neutralized or is made less basic. Then, a chemically amplified resist, containing an acid generator which produces an acid when irradiated with radiant rays and a compound reactive to acids, is applied to the semiconductor substrate, to form a resist film. This is followed by a step for sending radiant rays upon the resist film to expose it. Then, the exposed resist pattern is developed to form a resist pattern without footing or scumming and under-cutting.
    Type: Grant
    Filed: January 17, 1995
    Date of Patent: May 21, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akiko Katsuyama, Masaru Sasago, Kazuhiro Yamashita
  • Patent number: 5465066
    Abstract: A waveform formatter for use in testing a semiconductor device is capable of reducing a total size of circuit configuration. The waveform formatter includes a plurality of clock generators in which at low-speed operation, clocks are used to generate waveforms and control signals of drivers, while at high-speed operation, all clocks are used to generate waveforms for drivers. The waveform formatter further includes a parallel-serial converter for converting parallel signals to a serial signal, a data selector for selecting the parallel signals or the serial signal, and a waveform combining circuit for accepting output signals of the clock generators through a format control unit and for generating waveforms and control signals for the drivers using the clocks from the clock generators.
    Type: Grant
    Filed: September 21, 1994
    Date of Patent: November 7, 1995
    Assignee: Advantest Corporation
    Inventors: Kazuhiro Yamashita, Toshiyuki Negishi, Masatoshi Sato, Hiroshi Tsukahara
  • Patent number: 5252414
    Abstract: A method for evaluating a resist coating comprising the steps of: forming a first layer resist pattern including an alignment mark by applying a first resist on a semiconductor substrate and by exposing and developing said first resist, said first layer resist pattern having a ridge portion; irradiating said first layer resist pattern with a deep ultraviolet ray; applying, onto said irradiated first layer resist pattern, a second resist having substantially the same refractive index as said first resist to form a second resist coating; detecting said alignment mark formed in said first layer resist pattern, and relatively positioning a pattern for said second resist and said first layer resist pattern; and determining nonuniformity characteristics of said second resist coating by measuring an overlay accuracy between said first layer resist pattern and said pattern for said second resist.
    Type: Grant
    Filed: August 20, 1991
    Date of Patent: October 12, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiro Yamashita, Hironao Iwai, Noboru Nomura
  • Patent number: 5191465
    Abstract: An optical apparatus for aligning a reticle and a wafer together in connection with reduction projection onto the wafer of an image of a circuit pattern formed on the reticle. Two light beams having slightly different frequencies are concurrently applied to alignment gratings on the reticle and alignment gratings on the wafer through the windows on the reticle and a reduction projection lens. Heterodyne signals of interference rays resulting from diffraction by the alignment gratings on the reticle of the light applied to the alignment gratings are caught by a first optical sensor. Heterodyne signals of interference rays resulting from diffraction by the alignment gratings on the wafer of the light applied to the alignment gratings are caught by a second optical sensor. The difference in phase of the heterodyne signals detected by the respective optical sensors is detected by a phase meter, and the position of the wafer relative to the reticle is adjusted so that the phase difference is reduced to zero.
    Type: Grant
    Filed: September 5, 1991
    Date of Patent: March 2, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiro Yamashita, Noboru Nomura
  • Patent number: 5186788
    Abstract: Disclosed is a fine pattern forming method which is capable of forming a high positive-to-negative reversal pattern high in dry-etch resistance, at high density, by irradiating an entire surface of a resist with ion shower at low doses before or after electron beam or focus ion beam exposure, and then developing it.
    Type: Grant
    Filed: February 12, 1991
    Date of Patent: February 16, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Hashimoto, Kazuhiro Yamashita, Noboru Nomura
  • Patent number: 4870289
    Abstract: A system for controlling the relation in position between a photomask and a wafer for use in manufacturing apparatus of a highly integrated circuit such as large scale integration (LSI). The position control system includes a coherent light source for generating two light beams which are different in frequency and polarizing direction from each other. The light beams from the coherent light source is introduced into a first diffraction grating and the diffracted light from the first diffraction grating selectively pass through a telecentric lens system and are led to second and third diffraction gratings respectively disposed on the photomask and the wafer. Light beat signals are obtained in correspondance with the diffracted light from the second and third difraction gratings and the position relation between the photomask and wafer is controlled on the basis of the phase difference between the obtained light beat signals which corresponds to the position difference between the photomask and the wafer.
    Type: Grant
    Filed: September 23, 1988
    Date of Patent: September 26, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeo Sato, Shinichiro Aoki, Katsumasa Yamaguchi, Tadashi Kaneko, Noboru Nomura, Keisuke Koga, Kazuhiro Yamashita
  • Patent number: 4828392
    Abstract: A reduction projection type alignment and exposure apparatus which comprises a light source, a reticle having a first grating, first lens system, a spatial filter disposed around a Fourier spectral plane of the first lens system, second lens system, a substrate having a second grating, and a plurality of photo-detectors for detecting light intensities of a plurality of spectrums appearing on the spatial filter.The light beam generated from the light source is applied to the reticle at which it is divided into a plurality of diffracted light beams by the first grating, and the diffracted light beams are applied through the first lens system, the spatial filter and the second lens system onto the substrate so that the diffracted light beams are re-diffracted by the second grating, and the re-diffracted light beams appear as a plurality of spectrums on the spatial filter. These spectrums are detected by photo-detectors and used for alignment of the reticle and the substrate.
    Type: Grant
    Filed: March 10, 1986
    Date of Patent: May 9, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Noboru Nomura, Kazuhiro Yamashita, Takayoshi Matsumura, Midori Yamaguchi
  • Patent number: 4771180
    Abstract: A reduction projection type alignment and exposure apparatus having a light source, for alignment, a reticle having at least a first grating, first lens system, a spatial filter disposed around a Fourier spectral plane of the first lens system, second lens system, a wafer having at least a second grating, and a photo-detector for detecting light intensity of superimposed beams appearing on the spatial filter. An optical system for light exposure is provided separately from the optical system for alignment which includes the light source for alignment, first and second lens system, spatial filter, etc.
    Type: Grant
    Filed: October 8, 1986
    Date of Patent: September 13, 1988
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventors: Noboru Nomura, Kazuhiro Yamashita
  • Patent number: 4764206
    Abstract: A contradeglutitious solid herbicidal composition comprising a 1,1'-dimethyl-4,4'-bipyridylium salt in a substantially solid state and a thickening agent and, optionally, a water absorbable inorganic fine powder. This composition is difficult to swallow in its original form or even when diluted in a glass of water. The composition does not impair the inherent herbicidal effects and applicability of paraquat.
    Type: Grant
    Filed: February 13, 1986
    Date of Patent: August 16, 1988
    Assignee: S D S Bioteck K.K.
    Inventors: Kazuhiro Yamashita, Mamoru Yoshida