Abstract: A polar loop based radio telecommunication apparatus which has a phase control loop for controlling the phase of a carrier outputted from an oscillator for transmitter, and an amplitude control loop for controlling the amplitude of a transmission output signal outputted from a power amplifier circuit, wherein precharge means is provided on a forward path from a current source, through the power amplifier circuit, to a detection circuit, forming the amplitude control loop, for rapidly increasing a control voltage for the power amplifier circuit to a power threshold upon starting transmission.

Abstract: A food washing apparatus of the invention includes an ozonized water generator (10), a cylindrical washing tank (1) in which the food materials are put and which can rotate to wash the food materials, a drainage part (4) formed at a part of the washing tank (1) and including openings to such a degree that water passes through and the food materials do not pass through, and wash water pipings (2, 9) which are inserted and disposed in the washing tank (1) in an axial direction and in which water spray holes (2a, 2a) for spraying wash water including at least ozonized water are formed, and while at least one part of the wash water sprayed from the wash water pipings (2, 9) is draind from the washing tank (1) every rotation of the washing tank (1), washing of the food materials is performed.

Abstract: An A behavioral synthesis apparatus according to the present invention for performing a computer-automated synthesis of a circuit description of a register transfer level from a behavioral description describing a process operation of a circuit, wherein an output of a target computing unit is input to a plurality of subsequent computing units, and in the case when a valid cycle in which a result computed at each of the plurality of subsequent computing units is valid is different from each other, the behavioral synthesis apparatus including: a computing unit fixation section for inserting an input fixation unit between the target computing unit and at least one of the plurality of subsequent computing units, the input fixation unit fixing an input to the at least one subsequent computing unit during cycles other than the valid cycle in which a result computed at the at least one subsequent computing unit is valid.

Abstract: A polar loop based radio telecommunication apparatus which has a phase control loop for controlling the phase of a carrier outputted from an oscillator for transmitter, and an amplitude control loop for controlling the amplitude of a transmission output signal outputted from a power amplifier circuit, wherein precharge means is provided on a forward path from a current source, through the power amplifier circuit, to a detection circuit, forming the amplitude control loop, for rapidly increasing a control voltage for the power amplifier circuit to a power threshold upon starting transmission.

Abstract: A polar loop based radio telecommunication apparatus which has a phase control loop for controlling the phase of a carrier outputted from an oscillator for transmitter, and an amplitude control loop for controlling the amplitude of a transmission output signal outputted from a power amplifier circuit, wherein precharge means is provided on a forward path from a current source, through the power amplifier circuit, to a detection circuit, forming the amplitude control loop, for rapidly increasing a control voltage for the power amplifier circuit to a power threshold upon starting transmission.

Abstract: Disclosed is an apparatus for mobile communication system capable of constructing a system such as a mobile phone by setting a voltage corresponding to the characteristic variation of a PA even when a PA having characteristic variation is used. The mobile phone is the one employing the polar loop method, which comprises an antenna (1) for transmission and reception of signal waves; an antenna switch (2) for switching the transmission mode and the reception mode; a BBLSI (3) having a function to control the transmission and reception; an RFIC (4) having a function for modulating and demodulating the transmitted and received signals; and a PA (5) for amplifying up to the target output power by means of the amplitude modulation at the time of the transmission, wherein a bias voltage corresponding to the characteristic variation of the PA is set and supplied by a BIASDAC (6) formed of a register and a DAC so as to achieve the target output power at the time of the amplitude modulation in the PA.

Abstract: A behavioral synthesis system is provided, which includes a section for generating a control data flow graph from a behavioral description containing a loop process and a non-loop process, using nodes representing processing sections and input/output branches representing data flow, and a section for automatically synthesizing hardware structure at a register transfer level using the control data flow graph. A loop process portion of the control data flow graph represents that the nodes contained in the loop process are divided into pipelined stages and processes of the pipelined stages are executed in parallel in each of a plurality of the loop processes. The control data flow graph generating section includes, in the loop process portion, a loop control portion for outputting control signals for executing at least the non-loop process of the loop process and the non-loop process, to the nodes in the stages.

Abstract: A mobile communication system has a mobile phone in which a voltage is set corresponding to the characteristic variation of a PA even when a PA having characteristic variation is used. The mobile phone employs a polar loop method, which comprises an antenna (1) for transmission and reception of signal waves; an antenna switch (2) for switching the transmission mode and the reception mode; a BBLSI (3) having a function to control the transmission and reception; an RFIC (4) having a function for modulating and demodulating the transmitted and received signals; and a PA (5) for amplifying up to the target output power by means of the amplitude modulation at the time of the transmission.

Abstract: The present invention provides a semiconductor integrated circuit for communication (RF IC) realizing high yield without deteriorating a carrier leak characteristic even when a modulation circuit is formed by using cheep parts with large variations. In a semiconductor integrated circuit (RF IC) including: an input circuit constructed by a differential amplifier circuit and a level shifter, which is provided on the ante stage of a mixer of a differential circuit called a Gilbert Cell; and a modulation circuit that performs modulation by adding an I/Q signal and a carrier wave signal, a calibration circuit for canceling a DC offset in an output of the input circuit is provided.

Abstract: A compound represented by the following Formula (1) that is effective for the treatment of Paget's disease of bone or hypercalcemia or a medically acceptable solvate thereof; [wherein R1 refers to hydrogen atom, C1-C6 alkyl group optionally substituted with hydrogen group or C1-C6 alkoxy group optionally substituted with hydroxyl group, R2a and R2b refer to hydrogen atom, C1-C10 alkyl group optionally substituted with hydroxyl group, C6-C10 aryl group optionally substituted with hydroxyl group or C7-C12 aralkyl group optionally substituted with a hydroxyl group, or are combined to represent ethylene group. However, a compound in which R1 is a hydrogen atom or a methyl group and R2a and R2b are hydrogen atoms is excluded].

Abstract: The CDFG is generated by the CDFG generating section 109 based on the operation description of hardware 107, the CDFG is scheduled by the scheduling section 110 at an operation frequency required as the specification of the hardware and is assigned to each state, and the operation model of the hardware is generated by the cycle accurate model generating section 111 for each state as a description represented by a general-purpose programming language. The model which can be simulated for each state is generated by generating the operation model of each node using the operation information of the nodes included in the CDFG, and by determining the order in which the operation model of each node is calculated using the connection information of the nodes.

Abstract: A semiconductor integrated circuit with a PLL (Phase Locked Loop) built therein is used in a semiconductor integrated circuit for wireless communication. The PLL circuit generates an oscillation signal having a predetermined frequency, which is combined with a receive signal or a transmit signal for wireless communication. The PLL circuit includes a VCO capable of switching an oscillation frequency band, a variable divider, a loop filter and a phase comparator. An oscillation frequency of the VCO is controlled according to the difference in phase between a signal obtained by dividing the output of the VCO and a reference signal, and a discrimination circuit makes a decision as to a lead or delay of the phase of an output of the variable divider with respect to a reference signal having a predetermined frequency. An auto band selection circuit generates a signal for selecting a frequency band for the VCO.

Abstract: An arithmetic device allocation design method of the present invention includes the steps of: in the case of allocating an arithmetic operation A to the arithmetic device, comparing an increased circuit area due to a selector to be provided so as to allocate the operation A to an arithmetic device C to which another arithmetic operation B has already been allocated and an increased area due to an arithmetic device D to be created anew to which only the operation A is allocated; when the increased circuit area due to the selector is smaller, allocating the operation A to the device C to which the another operation B has already been allocated while providing the selector; and when the increased circuit area due to the device D is smaller, creating the device D anew so as to allocate the operation A to the device D created anew.

Abstract: A bus communication system for enabling data transfer in synchronized communication is provided, which comprises master circuits, a slave circuit, a bus, and a bus arbitration circuit. Data transfer is performed between the master circuits and the slave circuit via the bus. When a transfer request is output from the master circuits, the right to occupy the bus is given to the master circuit which continuously outputs the transfer request to the same address, not more than a predetermined number of times continuously. When receiving the transfer request from the master circuit, the slave circuit informs the master circuit of the end of bus transfer and whether or not data transfer is ready. When informed that data transfer is ready, the master circuit ends data transfer, and when informed that data transfer is not ready, the master circuit outputs a transfer request to the slave circuit again.

Abstract: An arithmetic device allocation design method of the present invention includes the steps of: in the case of allocating an arithmetic operation A to the arithmetic device, comparing an increased circuit area due to a selector to be provided so as to allocate the operation A to an arithmetic device C to which another arithmetic operation B has already been allocated and an increased area due to an arithmetic device D to be created anew to which only the operation A is allocated; when the increased circuit area due to the selector is smaller, allocating the operation A to the device C to which the another operation B has already been allocated while providing the selector; and when the increased circuit area due to the device D is smaller, creating the device D anew so as to allocate the operation A to the device D created anew.

Abstract: A behavioral synthesis system is provided, which comprising a section for generating a control data flow graph from a behavioral description containing a loop process and a non-loop process, using nodes representing processing sections and input/output branches representing data flow, and a section for automatically synthesizing hardware structure at a register transfer level using the control data flow graph. A loop process portion of the control data flow graph represents that the nodes contained in the loop process are divided into pipelined stages and processes of the pipelined stages are executed in parallel in each of a plurality of the loop processes. The control data flow graph generating section comprises, in the loop process portion, a loop control portion for outputting control signals for executing at least the non-loop process of the loop process and the non-loop process, to the nodes in the stages.

Abstract: When a transmitting oscillator is built in a communication semiconductor integrated circuit device like a high-frequency IC constituting a wireless communication system, the system prevents degradation of the accuracy of control on the output power of a power amplifier due to noise jumped from an output pin of the transmitting oscillator to an input pin for a detected signal (feedback signal) of an output level of the power amplifier. The transmitting oscillator is built in the high-frequency IC. The detected signal of the output level of the power amplifier, which is detected by a coupler, is attenuated to a level slightly higher than the level of noise jumped from the output pin of the transmitting oscillator to the input pin for a feedback signal of an amplitude control loop, which in turn is inputted to the feedback signal input pin of the high-frequency IC.

Abstract: Disclosed is an apparatus for mobile communication system capable of constructing a system such as a mobile phone by setting a voltage corresponding to the characteristic variation of a PA even when a PA having characteristic variation is used. The mobile phone is the one employing the polar loop method, which comprises an antenna (1) for transmission and reception of signal waves; an antenna switch (2) for switching the transmission mode and the reception mode; a BBLSI (3) having a function to control the transmission and reception; an RFIC (4) having a function for modulating and demodulating the transmitted and received signals; and a PA (5) for amplifying up to the target output power by means of the amplitude modulation at the time of the transmission, wherein a bias voltage corresponding to the characteristic variation of the PA is set and supplied by a BIASDAC (6) formed of a register and a DAC so as to achieve the target output power at the time of the amplitude modulation in the PA.

Abstract: A high level synthesis method for generating a logic circuit of a register transfer level from an operation description includes a control data flowgraph generation stage; a scheduling stage; an allocation stage; a data path generation stage; and a control logic generation stage. When generating a thread sharing a common memory with another thread operating in parallel therewith, a memory access request is represented by a node of a control data flowgraph so as to perform scheduling, and a control logic is generated. The control logic outputs a memory access request signal to a common memory interface in a state corresponding to a step to which the node is scheduled, and keeps the state until a memory access request acceptance signal from the common memory interface is changed to be active.

Abstract: A method for producing a biaxially stretched film is provided, in which the method comprises, stretching a film made mainly of an ethylene-vinyl alcohol copolymer having an ethylene content of 15 to 70 mol % and a saponification degree of 80 mol % or more under heating; cooling the film; and subjecting the cooled film to a heat treatment; wherein a heating temperature during the stretching is 60 to 160° C., a cooling temperature is a temperature 30 to 100° C. lower than the heating temperature during the stretching, and a temperature for the heat treatment is 150 to 190° C. The thus obtained biaxially stretched film of the present invention has a small bowing coefficient.