Patents by Inventor Kazuhito Higuchi
Kazuhito Higuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901185Abstract: According to an embodiment, an etching method includes forming a first layer on a substrate having a main surface including first and second regions adjacent to each other, the first layer including a portion covering the first region and having a plurality of openings or one or more openings defining a plurality of island-shaped portions, and the first layer further including a portion as a continuous layer covering the second region, forming a catalyst layer an a portion(s) of the main surface exposed in the openings by plating, forming a second layer to cover a portion of the catalyst layer adjacent to a boundary between the first and second regions and expose a portion of the catalyst layer spaced apart from the boundary, and etching the substrate in a presence of the catalyst layer and the second layer.Type: GrantFiled: September 13, 2021Date of Patent: February 13, 2024Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuo Sano, Susumu Obata, Kazuhito Higuchi, Takayuki Tajima
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Patent number: 11862667Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer.Type: GrantFiled: January 21, 2020Date of Patent: January 2, 2024Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Susumu Obata, Keiichiro Matsuo, Mitsuo Sano, Kazuhito Higuchi, Kazuo Shimokawa
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Publication number: 20230307184Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer therebetween, and first and second internal electrodes. The substrate has first and second main surfaces. One partial region of the first main surface is provided with first recesses. A region of the second surface corresponding to a combination of the one partial region and another partial region is provided with second recesses. The conductive layer covers the main surfaces and side walls and bottom surfaces of the recesses. The first internal electrode is provided on the one partial region and electrically connected to the conductive layer. The second internal electrode is provided on the another partial region and electrically connected to the substrate.Type: ApplicationFiled: May 10, 2023Publication date: September 28, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhito HIGUCHI, Kazuo SHIMOKAWA, Susumu OBATA, Mitsuo SANO
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Publication number: 20230298907Abstract: In general, according to one embodiment, there is provided a method of manufacturing a structure. The method includes forming a recess in a semiconductor substrate; oxidizing at least a bottom inner surface of the recess; and providing at least the bottom inner surface of the recess with a liquid capable of dissolving an oxide of a semiconductor substrate material.Type: ApplicationFiled: March 14, 2023Publication date: September 21, 2023Inventors: Mitsuo Sano, Susumu Obata, Kazuhito Higuchi, Takayuki Tajima
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Patent number: 11688557Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer therebetween, and first and second internal electrodes. The substrate has first and second main surfaces. One partial region of the first main surface is provided with first recesses. A region of the second surface corresponding to a combination of the one partial region and another partial region is provided with second recesses. The conductive layer covers the main surfaces and side walls and bottom surfaces of the recesses. The first internal electrode is provided on the one partial region and electrically connected to the conductive layer. The second internal electrode is provided on the another partial region and electrically connected to the substrate.Type: GrantFiled: August 20, 2020Date of Patent: June 27, 2023Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhito Higuchi, Kazuo Shimokawa, Susumu Obata, Mitsuo Sano
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Patent number: 11664231Abstract: According to one embodiment, there is provided a method for manufacturing a semiconductor device. The method includes metal electroplating on a surface of a first electrode formed on a first surface of a semiconductor substrate with a plating solution which contains aggregates of a supercritical fluid and a solution of a plating metal ion and an electrolyte. The first surface includes a recess. The surface is along with a shape of the recess. The recess has a first dimension and a second dimension, and assuming that an aspect ratio of the recess is given as a ratio of the second dimension to the first dimension, a median of a particle size distribution of the aggregates is greater than the first dimension.Type: GrantFiled: March 16, 2022Date of Patent: May 30, 2023Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Kazuhito Higuchi
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Publication number: 20230091900Abstract: According to one embodiment, an etching apparatus includes a first container including an opening covered by a semiconductor substrate; a second container including an opening covered by a catalyst layer; a first flow path configured to communicate with the first container; a second flow path configured to communicate with the second container; a cation exchange film interposed between the first flow path and the second flow path and allowing at least protons to pass through; and an electric field applier configured to apply an electric field to the semiconductor substrate.Type: ApplicationFiled: March 16, 2022Publication date: March 23, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takayuki TAJIMA, Kazuhito HIGUCHI, Susumu OBATA, Mitsuo SANO
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Publication number: 20230077915Abstract: According to one embodiment, an etching method includes etching a surface made of a semiconductor and having a catalyst layer formed on the surface, by an etching agent in contact with the surface. The catalyst layer contains noble metal. The etching agent contains an oxidizer, a corrosive agent, and a N-containing polymer agent.Type: ApplicationFiled: March 15, 2022Publication date: March 16, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuo SANO, Susumu OBATA, Kazuhito HIGUCHI, Takayuki TAJIMA
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Publication number: 20230084019Abstract: According to one embodiment, there is provided a method for manufacturing a semiconductor device. The method includes metal electroplating on a surface of a first electrode formed on a first surface of a semiconductor substrate with a plating solution which contains aggregates of a supercritical fluid and a solution of a plating metal ion and an electrolyte. The first surface includes a recess. The surface is along with a shape of the recess. The recess has a first dimension and a second dimension, and assuming that an aspect ratio of the recess is given as a ratio of the second dimension to the first dimension, a median of a particle size distribution of the aggregates is greater than the first dimension.Type: ApplicationFiled: March 16, 2022Publication date: March 16, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazuhito HIGUCHI
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Patent number: 11588059Abstract: A structural body according to an embodiment includes a conductive substrate. A main surface of the conductive substrate includes a first region and a second region adjacent to the first region and lower in height than the first region. The first region is provided with one or more recesses having a bottom, a position of which is lower than a position of the second region. A surface region of the conductive substrate on a side of the main surface includes a porous structure at a position between the second region and the one or more recesses.Type: GrantFiled: March 15, 2021Date of Patent: February 21, 2023Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuo Sano, Susumu Obata, Kazuhito Higuchi, Kazuo Shimokawa
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Patent number: 11551864Abstract: According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.Type: GrantFiled: February 22, 2021Date of Patent: January 10, 2023Assignee: Kabushiki Kaisha ToshibaInventors: Keiichiro Matsuo, Susumu Obata, Mitsuo Sano, Kazuhito Higuchi, Kazuo Shimokawa
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Patent number: 11508525Abstract: A capacitor according to an embodiment includes a substrate having a first surface and a second surface and provided with one or more first through holes each extending from the first surface to the second surface, a first conductive layer covering the first surface, the second surface, and side walls of the one or more first through holes, a second conductive layer facing the first surface, the second surface, and the side walls of the one or more first through holes, with the first conductive layer interposed therebetween, and a dielectric layer interposed between the first conductive layer and the second conductive layer.Type: GrantFiled: March 16, 2020Date of Patent: November 22, 2022Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhito Higuchi, Susumu Obata, Keiichiro Matsuo, Mitsuo Sano
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Publication number: 20220310582Abstract: According to an embodiment, a semiconductor device includes a layer stack including a conductive substrate containing semiconductor material and including a first main surface provided with one or more recesses and a second main surface opposite to the first main surface, a conductive layer covering at least part of the first main surface and side walls and bottom surfaces of the one or more recesses, and a dielectric layer interposed between the conductive substrate and the conductive layer, the conductive layer and a portion of the conductive substrate adjacent to the dielectric layer being an upper electrode and a lower electrode of a capacitor, respectively, an insulating layer provided on the capacitor or on the second main surface, and an inductor provided on the insulating layer at a position of the capacitor.Type: ApplicationFiled: September 13, 2021Publication date: September 29, 2022Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Susumu OBATA, Kazuhito HIGUCHI, Mitsuo SANO, Takayuki TAJIMA
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Publication number: 20220301877Abstract: According to an embodiment, an etching method includes forming a first layer on a substrate having a main surface including first and second regions adjacent to each other, the first layer including a portion covering the first region and having a plurality of openings or one or more openings defining a plurality of island-shaped portions, and the first layer further including a portion as a continuous layer covering the second region, forming a catalyst layer an a portion(s) of the main surface exposed in the openings by plating, forming a second layer to cover a portion of the catalyst layer adjacent to a boundary between the first and second regions and expose a portion of the catalyst layer spaced apart from the boundary, and etching the substrate in a presence of the catalyst layer and the second layer.Type: ApplicationFiled: September 13, 2021Publication date: September 22, 2022Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuo SANO, Susumu OBATA, Kazuhito HIGUCHI, Takayuki TAJIMA
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Patent number: 11411074Abstract: According to an embodiment, a structure includes a substrate including a semiconductor material, wherein the substrate is provided with one or more recesses each of which has a depth direction that is equal to a thickness direction of the substrate, and the one or more recesses include a sidewall on which a plurality of grooves each extending in the depth direction are provided.Type: GrantFiled: February 11, 2021Date of Patent: August 9, 2022Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuo Sano, Susumu Obata, Kazuhito Higuchi
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Patent number: 11322308Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer and a dielectric layer. The conductive substrate has a first main surface and a second main surface. The first main surface includes sub-regions. Each sub-region is provided with recesses or projections each having a shape extending in one direction and arranged in a width direction thereof. One or more of the sub-regions and another one or more of the sub-regions are different from each other in a length direction of the recesses or protrusions. The conductive layer covers sidewalls and bottom surfaces of the recesses or sidewalls and top surfaces of the projections. The dielectric layer is interposed between the conductive substrate and the conductive layer.Type: GrantFiled: August 20, 2020Date of Patent: May 3, 2022Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuo Sano, Susumu Obata, Kazuhito Higuchi, Kazuo Shimokawa
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Publication number: 20220115238Abstract: According to an embodiment, an etching method includes forming an uneven structure including a protruding portion on a surface of a semiconductor substrate, the protruding portion having a reverse tapered cross-sectional shape; forming a catalyst layer on the surface of the semiconductor substrate at a top surface of the protruding portion, the catalyst layer including a noble metal; and supplying an etching solution to the catalyst layer to etch the semiconductor substrate with an assist from the noble metal as a catalyst.Type: ApplicationFiled: June 24, 2021Publication date: April 14, 2022Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takayuki TAJIMA, Kazuhito HIGUCHI, Susumu OBATA, Mitsuo SANO
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Publication number: 20210299648Abstract: According to an embodiment, a method of forming a catalyst layer includes performing displacement plating on a substrate having a surface that is made of a semiconductor and includes a plurality of projections, thereby depositing a catalytic metal at positions of the plurality of projections.Type: ApplicationFiled: March 15, 2021Publication date: September 30, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Susumu OBATA, Mitsuo SANO, Keiichiro MATSUO, Kazuhito HIGUCHI, Kazuo SHIMOKAWA
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Publication number: 20210296513Abstract: A structural body according to an embodiment includes a conductive substrate. A main surface of the conductive substrate includes a first region and a second region adjacent to the first region and lower in height than the first region. The first region is provided with one or more recesses having a bottom, a position of which is lower than a position of the second region. A surface region of the conductive substrate on a side of the main surface includes a porous structure at a position between the second region and the one or more recesses.Type: ApplicationFiled: March 15, 2021Publication date: September 23, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuo SANO, Susumu OBATA, Kazuhito HIGUCHI, Kazuo SHIMOKAWA
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Publication number: 20210296432Abstract: According to an embodiment, a structure includes a substrate including a semiconductor material, wherein the substrate is provided with one or more recesses each of which has a depth direction that is equal to a thickness direction of the substrate, and the one or more recesses include a sidewall on which a plurality of grooves each extending in the depth direction are provided.Type: ApplicationFiled: February 11, 2021Publication date: September 23, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuo SANO, Susumu OBATA, Kazuhito HIGUCHI