Patents by Inventor Kazuhito Kobayashi

Kazuhito Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8438527
    Abstract: According to one embodiment, an original plate evaluation method is disclosed. The original plate includes a substrate and N patterns differing from one another in shape. The method includes selecting N1 patterns from the N patterns based on first criterion, obtaining measured values for the N1 patterns, performing a decision whether the obtained measured values satisfy first specification value, selecting N2 patterns from the N patterns based on second criterion, predicting shapes of transfer patterns corresponding to N2 patterns, performing a decision whether the predicted shapes satisfy second specification value, and evaluating the plate based on the decision.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satomi Nakamura, Toshiya Kotani, Kazuhito Kobayashi, Akiko Mimotogi, Chikaaki Kodama
  • Publication number: 20130055172
    Abstract: According to one embodiment, an original plate evaluation method is disclosed. The original plate includes a substrate and N patterns differing from one another in shape. The method includes selecting N1 patterns from the N patterns based on first criterion, obtaining measured values for the N1 patterns, performing a decision whether the obtained measured values satisfy first specification value, selecting N2 patterns from the N patterns based on second criterion, predicting shapes of transfer patterns corresponding to N2 patterns, performing a decision whether the predicted shapes satisfy second specification value, and evaluating the plate based on the decision.
    Type: Application
    Filed: March 22, 2012
    Publication date: February 28, 2013
    Inventors: Satomi Nakamura, Toshiya Kotani, Kazuhito Kobayashi, Akiko Mimotogi, Chikaaki Kodama
  • Patent number: 8209697
    Abstract: A resource allocation method, a resource allocation program, and a resource allocation apparatus in which a request reception server subjects an inputted SQL to a syntax analysis. At least one SQL process is extracted from the input SQL, and a resource cost of a database required by a BES (Back End Server) to perform the SQL process for each of one or more process types contained in the SQL process is calculated. Further, an allocation ratio is determined for allocating the resource of a request executing server to a virtualized server in accordance with a resource cost ratio required by each of the BES to execute the SQL process. Additionally, requests are made for execution of the respective BES on the virtualized server to which the resource has been allocated so as to execute the SQL process.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: June 26, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhito Kobayashi, Masaaki Narita, Akira Ito, Sansei Ooshima, Norihiro Hara
  • Patent number: 8108824
    Abstract: A pattern verification method according to an embodiment includes, dividing a pattern data region or a pattern formation region formed based on the pattern data to a plurality of unit regions, calculating a pattern area ratio with respect to each unit region, calculating differences in the amount of the pattern area ratio between each unit region and adjacent unit regions thereto, setting the number or density of measurement point with respect to each unit region to the pattern of the pattern data region or the pattern formation region according to the difference in the amount of pattern area ratio, measuring the pattern size at each measurement point, and verifying whether the size measurement value is within a predetermined range or not.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: January 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Hiromitsu Mashita, Kazuhito Kobayashi
  • Publication number: 20120020158
    Abstract: A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged with a first distance therebetween. The select gate line includes a first interconnection in the first direction, the first interconnection having a second line width larger than the first line width, and a second interconnection extending from an end portion of the first interconnection, the second interconnection having a third line width the same as the first line width. A first word-line adjacent to the select gate line is arranged having a second distance to the second interconnection, the second distance being (4N+1) times the first distance (N being an integer of 1 or more).
    Type: Application
    Filed: July 20, 2011
    Publication date: January 26, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tohru OZAKI, Mitsuhiro Noguchi, Hideaki Maekawa, Hiromitsu Mashita, Takafumi Taguchi, Kazuhito Kobayashi, Hidefumi Mukai, Hiroyuki Nitta
  • Patent number: 7990474
    Abstract: An image correction circuit capable of easily achieving adaptive color correction on the basis of a luminance correction amount is provided. An image correction circuit includes: a luminance correction section for performing luminance correction on input image data; and a color correction section for performing adaptive color correction on input image data on the basis of the following formula (1): Cout?Cin×[1+M×(?Y/L)]??(1) where Cout represents a chrominance signal after color correction, Cin represents a chrominance signal before color correction, M represents an adaptive color correction magnitude which is a fixed positive value, ?Y represents the total amount of luminance correction by the luminance correction section, L represents a fixed positive value satisfying L<(Ymax/2), and Ymax represents maximum luminance of input image data.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: August 2, 2011
    Assignee: Sony Corporation
    Inventors: Shigeru Harada, Kazuhito Kobayashi, Yoshifumi Dochi, Tomonori Tsutsumi
  • Publication number: 20110143271
    Abstract: A pattern generating method includes obtaining an on-substrate pattern by performing a process for forming the on-substrate pattern by simulation or experiment based on a design pattern of the on-substrate pattern formed by an imprint process using a template, employing the design pattern when a comparison result of the design pattern and obtained on-substrate pattern satisfies a predetermined condition, and correcting the design pattern to satisfy the predetermined condition when the comparison result does not satisfy the predetermined condition.
    Type: Application
    Filed: June 24, 2010
    Publication date: June 16, 2011
    Inventors: Takeshi KOSHIBA, Hidefumi Mukai, Kazuhito Kobayashi, Takumi Ota
  • Publication number: 20100289762
    Abstract: This invention aims to provide a transparent conductive laminate excellent in sliding durability, edge-writing durability, finger writing durability and light resistance and suitable as a movable electrode substrate for a touch panel. Further, it aims to provide a touch panel using the above transparent conductive laminate. This invention is a transparent conductive laminate that is a laminate formed by laminating a polymer film, a cured resin layer-1 and a transparent conductive layer in this order, the cured resin layer-1 having concavoconvex shapes formed by phase separation of two components and containing no fine particles that impart concavoconvex shapes, and the cured resin layer-1 having an arithmetic average roughness (Ra), measured according to JIS B0601-1994, of 0.05 ?m or more but less than 0.5 ?m and a ten-point average roughness (Rz), measured according to JIS B0601-1982, of 0.5 ?m or more but less than 2.0 ?m, and a touch panel using the transparent conductive laminate.
    Type: Application
    Filed: September 19, 2008
    Publication date: November 18, 2010
    Applicants: TEIJIN LIMITED
    Inventors: Haruhiko Ito, Koichi Ueda, Kazuhito Kobayashi, Hidefumi Kusuda
  • Patent number: 7816430
    Abstract: The present invention provides a resin composition for printed wiring board to be used for electronic devices in which operating frequency exceeds 1 GHz, and a varnish, a prepreg and a metal clad laminated board using the same. One invention of the present invention is a resin composition for printed wiring board containing a cyanate ester compound having 2 or more cyanate groups in the molecule and/or a prepolymer thereof, an epoxy resin containing at least one kind of an epoxy resin having a biphenyl structure in the molecule, and a varnish, a prepreg and a metal clad laminated board using the same.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: October 19, 2010
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Yasuyuki Mizuno, Daisuke Fujimoto, Hiroshi Shimizu, Kazuhito Kobayashi, Takayuki Sueyoshi
  • Publication number: 20090258446
    Abstract: A pattern verification method according to an embodiment includes, dividing a pattern data region or a pattern formation region formed based on the pattern data to a plurality of unit regions, calculating a pattern area ratio with respect to each unit region, calculating differences in the amount of the pattern area ratio between each unit region and adjacent unit regions thereto, setting the number or density of measurement point with respect to each unit region to the pattern of the pattern data region or the pattern formation region according to the difference in the amount of pattern area ratio, measuring the pattern size at each measurement point, and verifying whether the size measurement value is within a predetermined range or not.
    Type: Application
    Filed: April 9, 2009
    Publication date: October 15, 2009
    Inventors: Toshiya Kotani, Hiromitsu Mashita, Kazuhito Kobayashi
  • Publication number: 20090013325
    Abstract: A resource allocation method, a resource allocation program, and a resource allocation apparatus in which a request reception server subjects an inputted SQL to a syntax analysis, extracts at least one SQL process from the SQL, calculates a resource cost of a database required by the BES to perform the SQL process for each of process types contained in the SQL process, decides an allocation ratio for allocating the resource of a request executing server to a virtualized server in accordance with a resource cost ratio required by each of the BES to execute the SQL process, and requests for execution of the respective BES on the virtualized server to which the resource has been allocated so as to execute the SQL process.
    Type: Application
    Filed: January 30, 2008
    Publication date: January 8, 2009
    Inventors: Kazuhito KOBAYASHI, Masaaki Narita, Akira Ito, Sansei Ooshima, Norihiro Hara
  • Patent number: 7337426
    Abstract: There is disclosed a pattern correcting method comprising extracting a correction pattern, at least the one or more correction patterns being included in a first design pattern formed on a substrate, acquiring layout information from the first design pattern, the layout information affecting a finished plane shape of the correction pattern on the substrate, determining contents of correction onto the correction pattern on the basis of the layout information, generating a design pattern-2 corresponding to the layout information so as to be associated with the correction pattern, and correcting the correction pattern in accordance with the contents of correction corresponding to the design pattern-2.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: February 26, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Shigeki Nojima, Kazuhito Kobayashi
  • Publication number: 20070273793
    Abstract: An image correction circuit capable of easily achieving adaptive color correction on the basis of a luminance correction amount is provided. An image correction circuit includes: a luminance correction means for performing luminance correction on input image data; and a color correction means for performing adaptive color correction on input image data on the basis of the following formula (1): Cout?Cin×[1+M×(? Y/L)] ??(1) where Cout represents a chrominance signal after color correction, Cin represents a chrominance signal before color correction, M represents an adaptive color correction magnitude which is a fixed positive value, ? Y represents the total amount of luminance correction by the luminance correction means, L represents a fixed positive value satisfying L<(Ymax/2), and Ymax represents maximum luminance of input image data.
    Type: Application
    Filed: May 9, 2007
    Publication date: November 29, 2007
    Applicant: SONY CORPORATION
    Inventors: Shigeru Harada, Kazuhito Kobayashi, Yoshifumi Dochi, Tomonori Tsutsumi
  • Patent number: 7208539
    Abstract: The present invention relates to a thermosetting resin composition comprising: (1) a metal salt of a disubstituted phosphinic acid, and (2) a resin having a dielectric constant of 2.9 or less at a frequency of 1 GHz or more, and a prepreg and a laminated board using the same.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: April 24, 2007
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Shinji Tsuchikawa, Michitoshi Arata, Kenichi Tomioka, Kazuhito Kobayashi
  • Patent number: 7147450
    Abstract: An injection apparatus comprises a screw drive shaft, a motor which generates torque to rotate the screw, a speed reducer, and a power transmission mechanism. The power transmission mechanism has a first pulley on an output shaft of the motor, a second pulley on an input shaft of the speed reducer, and a belt passed around the first and second pulleys. The speed reducer is located between the second pulley and the screw drive shaft. The speed reducer is formed of a planetary gear mechanism, and both its input and output shafts are situated on an extension of an axis of the screw drive shaft.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: December 12, 2006
    Assignee: Toshiba Machine Co., Ltd.
    Inventors: Toshihiro Kasai, Kazuhito Kobayashi, Junsuke Kawai
  • Patent number: 7114949
    Abstract: Method for mold clamping of the present invention is capable of shortening a molding cycle without any initial setting works for an engaging position of a tie bars. The method is constituted the steps of moving the tie bars in the direction of mold closing during mold close operation, judging a relative moving speed between a movable die plate and the tie bar to be within a predetermined value, engaging the tie bars with the movable die plate mechanically by operating an engaging means when the relative moving speed is judged to be within the value, then further moving the movable die plate against a fixed die plate under engagement, and after contact of a movable mold with a fixed mold driving a mold clamping cylinder, thereby executing mold clamping operation.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: October 3, 2006
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventors: Makoto Nishizawa, Toshihiro Kasai, Kazuhito Kobayashi, Yukio Iimura
  • Publication number: 20060167189
    Abstract: The present invention provides a resin composition for printed wiring board to be used for electronic devices in which operating frequency exceeds 1 GHz, and a varnish, a prepreg and a metal clad laminated board using the same. One invention of the present invention is a resin composition for printed wiring board containing a cyanate ester compound having 2 or more cyanate groups in the molecule and/or a prepolymer thereof, an epoxy resin containing at least one kind of an epoxy resin having a biphenyl structure in the molecule, and a varnish, a prepreg and a metal clad laminated board using the same.
    Type: Application
    Filed: September 29, 2003
    Publication date: July 27, 2006
    Inventors: Yasuyuki Mizuno, Daisuke Fujimoto, Hiroshi Shimizu, Kazuhito Kobayashi, Takayuki Sueyoshi
  • Patent number: 7078106
    Abstract: A thermosetting resin composition comprising: (1) a copolymer resin comprising (a) a monomer unit and (b) a monomer unit respectively represented by the following general formulae (I) and (II): wherein R1 represents hydrogen, a halogen, or a C1–C5 hydrocarbon group; R2 represents a halogen or a C1–C5 hydrocarbon group; x is 0 to 3; and each of m and n is a natural number; and (2) a cyanate resin having at least two cyanate groups per molecule; is used to provide a printed wiring board material and a printed wiring board for electronic appliances, having a low dielectric constant and a low dielectric dissipation factor as well as improved heat resistance.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: July 18, 2006
    Assignee: Hitachi Chemical Co., LTD
    Inventors: Shinji Tsuchikawa, Kazuhito Kobayashi, Yasuyuki Mizuno, Daisuke Fujimoto, Nozomu Takano
  • Patent number: 7011511
    Abstract: An injection apparatus for industrial machine capable of high speed injection is provided with an injection barrel communicating with a cavity formed by at least a pair of mold dies and introducing mold material to an end portion on communicating side of the barrel, a screw for injection inserted in the barrel in which the screw is capable of reciprocating motion so as to inject and fill the mold material into the cavity, a support means holding an end of the screw opposite to the cavity and capable of moving in the direction of the reciprocating motion, a first drive mechanism including an electric servomotor for moving the support means in the direction of the reciprocating motion and a second drive mechanism for moving the first drive mechanism in the direction of the reciprocating motion.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: March 14, 2006
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventors: Makoto Nishizawa, Kazuhito Kobayashi, Junsuke Kawai
  • Publication number: 20050257188
    Abstract: There is disclosed a pattern correcting method comprising extracting a correction pattern, at least the one or more correction patterns being included in a first design pattern formed on a substrate, acquiring layout information from the first design pattern, the layout information affecting a finished plane shape of the correction pattern on the substrate, determining contents of correction onto the correction pattern on the basis of the layout information, generating a design pattern-2 corresponding to the layout information so as to be associated with the correction pattern, and correcting the correction pattern in accordance with the contents of correction corresponding to the design pattern-2.
    Type: Application
    Filed: April 27, 2005
    Publication date: November 17, 2005
    Inventors: Toshiya Kotani, Shigeki Nojima, Kazuhito Kobayashi