Patents by Inventor Kazuhito Narita
Kazuhito Narita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8665661Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: August 20, 2012Date of Patent: March 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20120317544Abstract: There is provided an information processing apparatus including a comparison unit for comparing intermediate code converted from a source code of the program being developed with an intermediate code of the program stored in a database in the system development. The information processing apparatus also includes a similarity calculation unit for calculating a similarity between the programs based on a comparison result obtained by the comparison unit. A narrowing-down process is performed for a candidate to be recommended using additional information as occasion demands. The present disclosure can apply to the information processing method.Type: ApplicationFiled: June 6, 2012Publication date: December 13, 2012Inventors: Yoriko KOMATSUZAKI, Hiroki Nagahama, Kazumi Sato, Kazuhito Narita
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Publication number: 20120314497Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: August 20, 2012Publication date: December 13, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 8259494Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: August 12, 2010Date of Patent: September 4, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 8248849Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: August 12, 2010Date of Patent: August 21, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20120011330Abstract: Provided is a memory management apparatus including a determiner configured to determine whether or not a pattern of writing data being data to be a target of an instruction of writing in a memory is a frequently-appearing pattern, and a setting unit configured to set a shared reference with respect to the writing data having the frequently-appearing pattern in a case where it is determined by the determiner that the pattern of the writing data is the frequently-appearing pattern and data of the frequently-appearing pattern has already been held in the memory.Type: ApplicationFiled: May 26, 2011Publication date: January 12, 2012Applicant: Sony CorporationInventors: Yasuhiro MATSUZAKI, Hiroki KAMINAGA, Kazuhito NARITA, Kazumi SATO
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Publication number: 20100309723Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: August 12, 2010Publication date: December 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20100309722Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: August 12, 2010Publication date: December 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 7787277Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: March 21, 2008Date of Patent: August 31, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20080170424Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: March 21, 2008Publication date: July 17, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 7359228Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: December 18, 2006Date of Patent: April 15, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 7297599Abstract: A method of fabricating a semiconductor device includes forming on a semiconductor substrate a gate electrode with a gate insulating film being interposed between the substrate and the electrode, forming an insulating film for element isolation protruding from a surface of the semiconductor substrate, forming an oxide film on the surface of the semiconductor substrate with the gate electrode and the element isolation insulating film having been formed, removing the oxide film in a region in which a self-aligned contact hole is to be formed while using a resist pattern for removing the oxide film formed in a region in which the self-aligned contact hole is formed, and etching a part of the element isolation insulating film protruding from the surface of the semiconductor substrate so that said part is substantially on a level with the surface of the semiconductor substrate, while using the resist pattern for removing the oxide film formed in the region in which the self-aligned contact hole is formed.Type: GrantFiled: September 7, 2005Date of Patent: November 20, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Norio Ohtani, Hirohisa Iizuka, Hiroaki Hazama, Kazuhito Narita, Eiji Kamiya
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Publication number: 20070190727Abstract: A method of manufacturing a nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit and also including forming a first well for a memory cell and a second well for the MOS transistor in a semiconductor substrate.Type: ApplicationFiled: April 9, 2007Publication date: August 16, 2007Inventors: Hiroaki Hazama, Seiichi Mori, Hirohisa Iizuka, Norio Ootani, Kazuhito Narita
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Patent number: 7238975Abstract: A nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit comprises a semiconductor substrate, isolation insulating films for defining a plurality of element formation regions, each of the isolation insulating films being buried in an isolation trench provided in the semiconductor substrate, a floating gate provided in each of the element formation regions via a first gate insulating film, a control gate provided on the floating gate via a second gate insulating film, and source and drain regions provided in the semiconductor substrate in self-alignment with the control gate, wherein the floating gate is self-aligned at an isolation end in a direction of a channel width, and comprises a plurality of polysilicon films.Type: GrantFiled: June 4, 2004Date of Patent: July 3, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Hiroaki Hazama, Seiichi Mori, Hirohisa Iizuka, Norio Ootani, Kazuhito Narita
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Publication number: 20070103958Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: December 18, 2006Publication date: May 10, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 7195968Abstract: A method of fabricating a semiconductor device includes forming a resist pattern so that an opening between select gates of a select gate transistor is formed in a memory cell region, implanting threshold-adjusting ions under the select gate with the resist pattern serving as a mask and removing an oxide film, forming a nitride film and an interlayer insulation film after the resist pattern has been removed, forming a resist pattern used to form a contact hole between the select gates and a contact hole for a transistor to be formed in the peripheral circuit region, the transistor having a higher breakdown voltage than a memory cell transistor and etching the interlayer insulation film, the nitride film and the gate insulation film individually with the resist pattern serving as a mask.Type: GrantFiled: May 11, 2005Date of Patent: March 27, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Eiji Kamiya, Hirohisa Iizuka, Hiroaki Hazama, Kazuhito Narita, Norio Ohtani
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Patent number: 7151685Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: January 12, 2006Date of Patent: December 19, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20060120130Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: January 12, 2006Publication date: June 8, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20060051908Abstract: A method of fabricating a semiconductor device includes forming on a semiconductor substrate a gate electrode with a gate insulating film being interposed between the substrate and the electrode, forming an insulating film for element isolation protruding from a surface of the semiconductor substrate, forming an oxide film on the surface of the semiconductor substrate with the gate electrode and the element isolation insulating film having been formed, removing the oxide film in a region in which a self-aligned contact hole is to be formed while using a resist pattern for removing the oxide film formed in a region in which the self-aligned contact hole is formed, and etching a part of the element isolation insulating film protruding from the surface of the semiconductor substrate so that said part is substantially on a level with the surface of the semiconductor substrate, while using the resist pattern for removing the oxide film formed in the region in which the self-aligned contact hole is formed.Type: ApplicationFiled: September 7, 2005Publication date: March 9, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Norio Ohtani, Hirohisa Iizuka, Hiroaki Hazama, Kazuhito Narita, Eiji Kamiya
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Patent number: 7002845Abstract: A semiconductor memory device capable of preventing occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array and realizing an inexpensive chip having high operation reliability and high manufacturing yield is provided. A first block is constructed by first memory cell units each having a plurality of memory cells connected, a second block is constructed by second memory cell units each having a plurality of memory cells connected, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit.Type: GrantFiled: October 5, 2004Date of Patent: February 21, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome