Patents by Inventor Kazuhito Narita
Kazuhito Narita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050253202Abstract: A semiconductor device includes a semiconductor substrate, a plurality of memory cell transistors and select gate transistors both formed in a memory cell region of the semiconductor substrate, and a transistor formed in a peripheral circuit region of the substrate and having a high breakdown voltage. Each select gate transistor of the memory cell region has a gate electrode under which an ion implanted layer is formed for adjustment of a threshold. The transistor having the high breakdown voltage includes a contact region around which a gate insulation film remains.Type: ApplicationFiled: May 11, 2005Publication date: November 17, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Eiji Kamiya, Hirohisa Iizuka, Hiroaki Hazama, Kazuhito Narita, Norio Ohtani
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Patent number: 6933194Abstract: A method of manufacturing a semiconductor device including forming a laminate structure which includes a gate insulation film on a semiconductor substrate and a gate electrode material film on the gate insulation film, processing the gate electrode material film to obtain a gate electrode having a reverse tapered cross section, and forming a device isolation insulation film in direct contact with a side surface of the gate electrode.Type: GrantFiled: September 26, 2003Date of Patent: August 23, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhito Narita, Eiji Sakagami, Hiroaki Tsunoda, Masahisa Sonoda, Hideyuki Kobayashi
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Publication number: 20050063209Abstract: A semiconductor memory device capable of preventing occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array and realizing an inexpensive chip having high operation reliability and high manufacturing yield is provided. A first block is constructed by first memory cell units each having a plurality of memory cells connected, a second block is constructed by second memory cell units each having a plurality of memory cells connected, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit.Type: ApplicationFiled: October 5, 2004Publication date: March 24, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20050012142Abstract: A nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit comprises a semiconductor substrate, isolation insulating films for defining a plurality of element formation regions, each of the isolation insulating films being buried in an isolation trench provided in the semiconductor substrate, a floating gate provided in each of the element formation regions via a first gate insulating film, a control gate provided on the floating gate via a second gate insulating film, and source and drain regions provided in the semiconductor substrate in self-alignment with the control gate, wherein the floating gate is self-aligned at an isolation end in a direction of a channel width, and comprises a plurality of polysilicon films.Type: ApplicationFiled: June 4, 2004Publication date: January 20, 2005Inventors: Hiroaki Hazama, Seiichi Mori, Hirohisa Iizuka, Norio Ootani, Kazuhito Narita
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Patent number: 6836444Abstract: A semiconductor memory device includes a memory cell array comprising memory cell units arranged in an array form, first blocks including first memory cell units each having at least one memory cell and at least one selection gate transistor, and second blocks including second memory cell units each having at least one memory cell and at least one selection gate transistor, wherein the first blocks are arranged on both end portions of the memory cell array, the second blocks are arranged in another portion, and a structure of the first memory cell units on the end portions of the memory cell array is different from a structure of the second memory cell units.Type: GrantFiled: June 3, 2003Date of Patent: December 28, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20040063266Abstract: This invention provides a semiconductor device including a semiconductor substrate, a transistor having a gate insulation film on the semiconductor substrate and a gate electrode on the gate insulation film, and a device isolating insulation film having a first portion which extends from a surface of the semiconductor substrate to an inner part of the semiconductor substrate and a second portion which protrudes from the semiconductor substrate, wherein a side surface of the second portion is in direct contact with a side surface of the gate electrode at least partially and a cross section of the gate electrode is reverse tapered. This invention also provides a manufacturing method thereof.Type: ApplicationFiled: September 26, 2003Publication date: April 1, 2004Inventors: Kazuhito Narita, Eiji Sakagami, Hiroaki Tsunoda, Masahisa Sonoda, Hideyuki Kobayashi
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Publication number: 20030206439Abstract: A semiconductor memory device capable of preventing occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array and realizing an inexpensive chip having high operation reliability and high manufacturing yield is provided. A first block is constructed by first memory cell units each having a plurality of memory cells connected, a second block is constructed by second memory cell units each having a plurality of memory cells connected, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit.Type: ApplicationFiled: June 3, 2003Publication date: November 6, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 6642568Abstract: This invention provides a semiconductor device including a semiconductor substrate, a transistor having a gate insulation film on the semiconductor substrate and a gate electrode on the gate insulation film, and a device isolating insulation film having a first portion which extends from a surface of the semiconductor substrate to an inner part of the semiconductor substrate and a second portion which protrudes from the semiconductor substrate, wherein a side surface of the second portion is in direct contact with a side surface of the gate electrode at least partially and a cross section of the gate electrode is reverse tapered. This invention also provides a manufacturing method thereof.Type: GrantFiled: June 28, 2001Date of Patent: November 4, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhito Narita, Eiji Sakagami, Hiroaki Tsunoda, Masahisa Sonoda, Hideyuki Kobayashi
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Patent number: 6611447Abstract: A semiconductor memory device capable of preventing occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array and realizing an inexpensive chip having high operation reliability and high manufacturing yield is provided. A first block is constructed by first memory cell units each having a plurality of memory cells connected, a second block is constructed by second memory cell units each having a plurality of memory cells connected, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit.Type: GrantFiled: June 12, 2002Date of Patent: August 26, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20020154529Abstract: A semiconductor memory device capable of preventing occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array and realizing an inexpensive chip having high operation reliability and high manufacturing yield is provided. A first block is constructed by first memory cell units each having a plurality of memory cells connected, a second block is constructed by second memory cell units each having a plurality of memory cells connected, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit.Type: ApplicationFiled: June 12, 2002Publication date: October 24, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 6462373Abstract: In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.Type: GrantFiled: November 30, 2000Date of Patent: October 8, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Shimizu, Riichiro Shirota, Naoki Koido, Seiichi Aritome, Hiroaki Tsunoda, Tadashi Iguchi, Kazuhito Narita, Kunihiro Terasaka, Hirohisa Iizuka
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Patent number: 6424588Abstract: A semiconductor memory device capable of preventing occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array and realizing an inexpensive chip having high operation reliability and high manufacturing yield is provided. A first block is constructed by first memory cell units each having a plurality of memory cells connected, a second block is constructed by second memory cell units each having a plurality of memory cells connected, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit.Type: GrantFiled: December 28, 2000Date of Patent: July 23, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 6413809Abstract: A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.Type: GrantFiled: March 8, 2001Date of Patent: July 2, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Takuya Nakamura, Naoki Koido, Hirohisa Iizuka, Kazuhito Narita, Seiichi Aritome, Fumitaka Arai
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Publication number: 20020030223Abstract: This invention provides a semiconductor device including a semiconductor substrate, a transistor having a gate insulation film on the semiconductor substrate and a gate electrode on the gate insulation film, and a device isolating insulation film having a first portion which extends from a surface of the semiconductor substrate to an inner part of the semiconductor substrate and a second portion which protrudes from the semiconductor substrate, wherein a side surface of the second portion is in direct contact with a side surface of the gate electrode at least partially and a cross section of the gate electrode is reverse tapered. This invention also provides a manufacturing method thereof.Type: ApplicationFiled: June 28, 2001Publication date: March 14, 2002Inventors: Kazuhito Narita, Eiji Sakagami, Hiroaki Tsunoda, Masahisa Sonoda, Hideyuki Kobayashi
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Patent number: 6342715Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to bType: GrantFiled: June 15, 1998Date of Patent: January 29, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Shimizu, Seiichi Aritome, Toshiharu Watanabe, Kazuhito Narita
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Patent number: 6340611Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to bType: GrantFiled: July 28, 2000Date of Patent: January 22, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Shimizu, Seiichi Aritome, Toshiharu Watanabe, Kazuhito Narita
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Publication number: 20010019508Abstract: In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.Type: ApplicationFiled: November 30, 2000Publication date: September 6, 2001Inventors: Kazuhiro Shimizu, Riichiro Shirota, Naoki Koido, Seiichi Aritome, Hiroaki Tsunoda, Tadashi Iguchi, Kazuhito Narita, Kunihiro Terasaka, Hirohisa Iizuka
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Publication number: 20010018253Abstract: A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.Type: ApplicationFiled: March 8, 2001Publication date: August 30, 2001Inventors: Takuya Nakamura, Naoki Koido, Hirohisa Iizuka, Kazuhito Narita, Seiichi Aritome, Fumitaka Arai
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Patent number: 6258665Abstract: The non-volatile semiconductor memory device is formed on a silicon substrate and comprises a plurality of semiconductor active regions defined by a plurality of element isolation regions, a source region and a drain region formed in each of the semiconductor active regions, a charge storage layer which capacitively couples to the semiconductor active region between the source region and the drain region, and a control gate which capacitively couples to the charge storage layer through a second gate insulation film, wherein the second gate insulation film is left extending from the upper surface portion of the element isolation region which lies under the control gate to the upper surface portion of the element isolation region other than the upper surface portion of the element isolation region lying under the control gate.Type: GrantFiled: March 21, 2000Date of Patent: July 10, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Shimizu, Seiichi Aritome, Kazuhito Narita
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Patent number: 6240012Abstract: A semiconductor memory device capable of preventing occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array and realizing an inexpensive chip having high operation reliability and high manufacturing yield is provided. A first block is constructed by first memory cell units each having a plurality of memory cells connected, a second block is constructed by second memory cell units each having a plurality of memory cells connected, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit.Type: GrantFiled: July 1, 1999Date of Patent: May 29, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome