Abstract: In the portable telephone of the present invention, a transmission power upper limit value (STEPLIM in accordance with temperature (T) is found (S1, S2), whether the transmission power set value (STEPn) of the next slot exceeds the upper limit (STEPLIM) or not is determined (S3, S4), and when it does not exceed, a control signal value (Vc) in accordance with the transmission power set value (STEPn) is applied to a variable gain block (11, 13) (S5, S7). When it exceeds the upper limit, a control signal value (Vc) in accordance with the transmission power upper limit value (STEPLIM) is applied to the variable gain block (11, 13) (S6, S7).

Abstract: A radio transmitter includes a gain compensation controller that derives the gain variation of the power amplifier from its bias voltage determined in response to its desired output power level, and that derives the control voltage of at least one of variable gain amplifiers from the gain variation. A variable gain amplifier gain controller applies the control voltage to the variable gain amplifier, thereby compensating for the gain variation of the power amplifier. The radio transmitter can solve a problem of a conventional radio transmitter in that it is unavoidable for the power amplifier to bring about the gain variation when its bias voltage is varied in response to the output power level.

Abstract: Disclosed is a semiconductor device including a bipolar transistor and a field effect transistor and allowing an increased operating speed, and a method of manufacturing such a semiconductor device. In the semiconductor device, a junction depth of an intrinsic base layer and a junction depth of an external base layer are made shallower than a junction depth of source/drain regions. Whereby a parasitic capacitance of the bipolar transistor portion is reduced, and at the same time, a driving current of the field effect transistor portion is increased to some extent. Consequently, an increased operating speed of the bipolar transistor portion and the field effect transistor portion is achieved.

Abstract: An n type buried layer (2b) lying in the lower part of a PNP transistor (101a) is lower in impurity concentration than an n.sup.+ type buried layer (2a) lying in the lower part of an NPN transistor (100). A p.sup.+ type buried layer (4a) is formed thick on the n type buried layer (2b) and insulated from the n.sup.+ type buried layer (2a) by an isolation trench (7). A breakdown voltage at a junction of the p.sup.+ type buried layer (4a) and the n type buried layer (2b) can be improved and, accordingly, the breakdown voltage of the whole device being improved. Low-controlled collector resistance of the PNP transistor (101a) prevents an amplification factor from decreasing.

Abstract: An n type buried layer (2b) lying in the lower part of a PNP transistor (101a) is lower in impurity concentration than an n.sup.+ type buried layer (2a) lying in the lower part of an NPN transistor (100). A p.sup.+ type buried layer (4a) is formed thick on the n type buried layer (2b) and insulated from the n.sup.+ type buried layer (2a) by an isolation trench (7). A breakdown voltage at a junction of the p.sup.+ type buried layer (4a) and the n type buried layer (2b) can be improved and, accordingly, the breakdown voltage of the whole device being improved. Low-controlled collector resistance of the PNP transistor (101a) prevents an amplification factor from decreasing.

Abstract: According to the present invention, a second conductivity type subcollector layer and a second conductivity type collector layer are sequentially formed on a first conductivity type semiconductor substrate and thereafter first and second insulation layers are simultaneously formed in a region corresponding to a memory element area and regions corresponding to prescribed regions of a peripheral circuit area within an upper layer part of the second conductivity type collector layer. Thus, the degree of integration is improved by simplification of manufacturing steps and reduction of the number of masking times.