Patents by Inventor Kazuki Fukuoka
Kazuki Fukuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150076709Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.Type: ApplicationFiled: November 8, 2014Publication date: March 19, 2015Inventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
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Publication number: 20150046729Abstract: First and second processing units execute a binary program. A temperature sensor measures a temperature of a first processing unit. A temperature detection unit outputs a first interrupt instruction when the temperature measured by the temperature sensor exceeds a first value. A bus exchanges data between the first and second processing units. In response to the first interrupt instruction, the control unit interrupts execution in the first processing unit, migrates first data that is necessary for resuming the execution of the binary program from the first processing unit to the second processing unit, and controls the second processing unit to resume the execution of the binary program in the second processing unit. A power control unit interrupts power supply to the first processing unit after the first data is migrated to the second processing unit.Type: ApplicationFiled: August 7, 2014Publication date: February 12, 2015Inventors: Kazuki FUKUOKA, Kazuo OTSUGA
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Patent number: 8896129Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.Type: GrantFiled: February 15, 2013Date of Patent: November 25, 2014Assignee: Renesas Electronics CorporationInventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
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Patent number: 8730703Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.Type: GrantFiled: January 24, 2013Date of Patent: May 20, 2014Assignee: Renesas Electronics CorporationInventors: Kazuki Fukuoka, Yasuto Igarashi, Ryo Mori, Yoshihiko Yasu, Toshio Sasaki
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Publication number: 20130256906Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.Type: ApplicationFiled: February 15, 2013Publication date: October 3, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
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Patent number: 8421527Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.Type: GrantFiled: July 30, 2012Date of Patent: April 16, 2013Assignee: Renesas Electronics CorporationInventors: Toshio Sasaki, Kazuki Fukuoka, Ryo Mori, Yoshihiko Yasu
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Patent number: 8379425Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.Type: GrantFiled: February 26, 2010Date of Patent: February 19, 2013Assignee: Renesas Electronics CorporationInventors: Kazuki Fukuoka, Yasuto Igarashi, Ryo Mori, Yoshihiko Yasu, Toshio Sasaki
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Publication number: 20120293247Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.Type: ApplicationFiled: July 30, 2012Publication date: November 22, 2012Inventors: Toshio SASAKI, Kazuki FUKUOKA, Ryo MORI, Yoshihiko YASU
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Patent number: 8253481Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.Type: GrantFiled: September 25, 2011Date of Patent: August 28, 2012Assignee: Renesas Electronics CorporationInventors: Toshio Sasaki, Kazuki Fukuoka, Ryo Mori, Yoshihiko Yasu
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Publication number: 20120013382Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.Type: ApplicationFiled: September 25, 2011Publication date: January 19, 2012Inventors: Toshio SASAKI, Kazuki Fukuoka, Ryo Mori, Yoshihiko Yasu
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Patent number: 8044709Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.Type: GrantFiled: October 29, 2009Date of Patent: October 25, 2011Assignee: Renesas Electronics CorporationInventors: Toshio Sasaki, Kazuki Fukuoka, Ryo Mori, Yoshihiko Yasu
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Publication number: 20110175664Abstract: A power-supply sequence-free electronic circuit is realized without the increase of the number of power supply detectors for detecting the rising of the power supply. The electronic circuit operated by supplying three or more types of power supply voltages to the ground voltage of the circuit generates a first detection signal indicating whether any one of other power supply voltages does not rise by a first detection circuit which is operated with a predetermined power supply voltage as an operation power supply. The electronic circuit generates a second detection signal indicating whether the predetermined power supply voltage rises by a second detection circuit which is provided for each of the other power supply voltages and operated with one power supply voltage of the other power supply voltages as an operation power supply.Type: ApplicationFiled: January 10, 2011Publication date: July 21, 2011Inventors: Junpei INOUE, Naoki YADA, Sadayuki MORITA, Kazuki FUKUOKA
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Publication number: 20100219800Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.Type: ApplicationFiled: February 26, 2010Publication date: September 2, 2010Inventors: Kazuki FUKUOKA, Yasuto Igarashi, Ryo Mori, Yoshihiko Yasu, Toshio Sasaki
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Publication number: 20100123515Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.Type: ApplicationFiled: October 29, 2009Publication date: May 20, 2010Inventors: TOSHIO SASAKI, Kazuki Fukuoka, Ryo Mori, Yoshihiko Yasu