Patents by Inventor Kazuki Fukuoka

Kazuki Fukuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150076709
    Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.
    Type: Application
    Filed: November 8, 2014
    Publication date: March 19, 2015
    Inventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
  • Publication number: 20150046729
    Abstract: First and second processing units execute a binary program. A temperature sensor measures a temperature of a first processing unit. A temperature detection unit outputs a first interrupt instruction when the temperature measured by the temperature sensor exceeds a first value. A bus exchanges data between the first and second processing units. In response to the first interrupt instruction, the control unit interrupts execution in the first processing unit, migrates first data that is necessary for resuming the execution of the binary program from the first processing unit to the second processing unit, and controls the second processing unit to resume the execution of the binary program in the second processing unit. A power control unit interrupts power supply to the first processing unit after the first data is migrated to the second processing unit.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 12, 2015
    Inventors: Kazuki FUKUOKA, Kazuo OTSUGA
  • Patent number: 8896129
    Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: November 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
  • Patent number: 8730703
    Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: May 20, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuki Fukuoka, Yasuto Igarashi, Ryo Mori, Yoshihiko Yasu, Toshio Sasaki
  • Publication number: 20130256906
    Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.
    Type: Application
    Filed: February 15, 2013
    Publication date: October 3, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
  • Patent number: 8421527
    Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: April 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Toshio Sasaki, Kazuki Fukuoka, Ryo Mori, Yoshihiko Yasu
  • Patent number: 8379425
    Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: February 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuki Fukuoka, Yasuto Igarashi, Ryo Mori, Yoshihiko Yasu, Toshio Sasaki
  • Publication number: 20120293247
    Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.
    Type: Application
    Filed: July 30, 2012
    Publication date: November 22, 2012
    Inventors: Toshio SASAKI, Kazuki FUKUOKA, Ryo MORI, Yoshihiko YASU
  • Patent number: 8253481
    Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: August 28, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshio Sasaki, Kazuki Fukuoka, Ryo Mori, Yoshihiko Yasu
  • Publication number: 20120013382
    Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.
    Type: Application
    Filed: September 25, 2011
    Publication date: January 19, 2012
    Inventors: Toshio SASAKI, Kazuki Fukuoka, Ryo Mori, Yoshihiko Yasu
  • Patent number: 8044709
    Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: October 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshio Sasaki, Kazuki Fukuoka, Ryo Mori, Yoshihiko Yasu
  • Publication number: 20110175664
    Abstract: A power-supply sequence-free electronic circuit is realized without the increase of the number of power supply detectors for detecting the rising of the power supply. The electronic circuit operated by supplying three or more types of power supply voltages to the ground voltage of the circuit generates a first detection signal indicating whether any one of other power supply voltages does not rise by a first detection circuit which is operated with a predetermined power supply voltage as an operation power supply. The electronic circuit generates a second detection signal indicating whether the predetermined power supply voltage rises by a second detection circuit which is provided for each of the other power supply voltages and operated with one power supply voltage of the other power supply voltages as an operation power supply.
    Type: Application
    Filed: January 10, 2011
    Publication date: July 21, 2011
    Inventors: Junpei INOUE, Naoki YADA, Sadayuki MORITA, Kazuki FUKUOKA
  • Publication number: 20100219800
    Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 2, 2010
    Inventors: Kazuki FUKUOKA, Yasuto Igarashi, Ryo Mori, Yoshihiko Yasu, Toshio Sasaki
  • Publication number: 20100123515
    Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.
    Type: Application
    Filed: October 29, 2009
    Publication date: May 20, 2010
    Inventors: TOSHIO SASAKI, Kazuki Fukuoka, Ryo Mori, Yoshihiko Yasu