Patents by Inventor Kazuki HYOUDOU

Kazuki HYOUDOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11880724
    Abstract: An apparatus includes: a storing device including regions allocated one to each of virtual machines; a processing device, connected to the storing device, that executes the virtual machines; a relay device, connected to the processing device, that executes a relaying process, serving as a virtual switch that connects the virtual machines to one another; and a transfer processor that transfers data between the regions through the processing device. The relay device obtains, from a first region, a first fragment data of target data being stored in the first region and indicating a destination of the target data, and outputs, when the destination is a second region, an instruction instructing the transfer processor to transfer the target data from the first region to the second region. The transfer processor transfers the target data from the first region to the second region through the processing device in response to the instruction.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: January 23, 2024
    Assignee: FUJITSU LIMITED
    Inventor: Kazuki Hyoudou
  • Publication number: 20230004509
    Abstract: An information processing device includes a field programmable gate array configured to store route information in flow control, and forward packets according to the route information; one or more memories configured to store a flow cache that includes at least a part of the route information; and one or more processors coupled to the one or more memories and the one or more processors configured to divide the route information into a plurality of division areas; and acquire hit information extracted from each of the entries in a first division area of the plurality of division areas to delete a part of entries of the flow cache stored in the one or more memories, the first division area including flows whose number is greater than a threshold value.
    Type: Application
    Filed: April 26, 2022
    Publication date: January 5, 2023
    Applicant: FUJITSU LIMITED
    Inventor: Kazuki Hyoudou
  • Publication number: 20220263757
    Abstract: An apparatus includes: a storing device including storing regions allocated to virtual machines; a processing device being connected to the storing device and executing the virtual machines; a relay device being connected to the processing device and executing a relaying process serving as a virtual switch that connects virtual machines to one another; and a transfer processor that forwards data between storing regions. The processing device determines whether a header of transmission target data being stored in a first storing region among the storing regions satisfies a given condition. When the header satisfies the given condition, the transfer processor forwards the transmission target data from the first to a second storing region serving as a destination of the transmission target data through a path not being used for the relaying process performed by the relay device.
    Type: Application
    Filed: November 12, 2021
    Publication date: August 18, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Ryo Miyashita, Kazuki Hyoudou
  • Publication number: 20220029914
    Abstract: An apparatus includes: a storing device including regions allocated one to each of virtual machines; a processing device, connected to the storing device, that executes the virtual machines; a relay device, connected to the processing device, that executes a relaying process, serving as a virtual switch that connects the virtual machines to one another; and a transfer processor that transfers data between the regions through the processing device. The relay device obtains, from a first region, a first fragment data of target data being stored in the first region and indicating a destination of the target data, and outputs, when the destination is a second region, an instruction instructing the transfer processor to transfer the target data from the first region to the second region. The transfer processor transfers the target data from the first region to the second region through the processing device in response to the instruction.
    Type: Application
    Filed: April 8, 2021
    Publication date: January 27, 2022
    Applicant: FUJITSU LIMITED
    Inventor: Kazuki Hyoudou
  • Publication number: 20210089343
    Abstract: An information processing apparatus includes a memory configured to include a reception buffer in which data destined for a virtual machine that operates in the information processing apparatus is written, and a processor coupled to the memory and configured to continuously allocate a first storage area of the reception buffer to a first coprocessor which is an offload destination of a relay process of a virtual switch, and allocate a second storage area of the reception buffer to a second coprocessor which is an offload destination of an extension process of the virtual switch when an allocation request of the reception buffer is received from the second coprocessor.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 25, 2021
    Applicant: FUJITSU LIMITED
    Inventor: Kazuki Hyoudou
  • Patent number: 10944677
    Abstract: An information processing apparatus includes a plurality of offload devices each of which offloads and executes a relay process of a virtual switch, each of the plurality of offload devices including a memory that stores port conversion information, the port conversion information associating virtual port identifiers for identifying virtual ports before and after a virtual port to which a virtual machine executed by the information processing apparatus is connected is moved between the offload devices, and a processor coupled to the memory and that converts an input virtual port identifier for identifying an input virtual port into which a packet is input based on the port conversion information, searches an output virtual port identifier for identifying an output virtual port of the packet by using the converted input virtual port identifier, and converts the searched output virtual port identifier based on the port conversion information.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: March 9, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Kazuki Hyoudou
  • Patent number: 10791061
    Abstract: A communication control device includes one or more memories configured to store log information indicating an input port through which a packet included in one of flows are inputted, an output port through which the packet is outputted, and time related to input of the packet, and one or more processors coupled to the one or more memories and the one or more processors configured to, on the basis of the log information, perform generation of relation information indicating relations among the flows, and when a first port is in a congested state, identify, in accordance with the relation information, an original flow on which a first flow is based, the first flow regarding a first packet included in an output queue of the first port.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 29, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kazuki Hyoudou
  • Patent number: 10558485
    Abstract: A non-transitory computer-readable recording medium storing a program that causes a computer including a first-processor in which a first-thread is executed at a first-node having a first-buffer and a communication device and a second-processor in which a second-thread is executed at a second-node having a second-buffer, the first-thread includes setting an output-destination of the communication device to the second-buffer with respect to a flow addressed to a virtual machine executed in the second-processor, notifying the second-processor of a switch notification information of the setting the output-destination of the communication device to the second-buffer, and transferring a packet stored in the first-buffer to the second-processor, and the second-thread includes receiving the switching notification, suspending temporarily a reception-process of the second-buffer for the flow, transferring the packet transferred by the first-processor to the virtual machine, and resuming the reception-process of the se
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: February 11, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kazuki Hyoudou
  • Patent number: 10541861
    Abstract: A system includes a first switch, a second switch, and a processing device. The first switch detects a failure occurring at a first port, generates failure information on the first port when the failure occurring at the first port is detected, and transmits a failure notification packet including the failure information to another switch through a port other than the first port. The second switch transmits a selection-condition-added packet through a port which is coupled to the processing device, the selection-condition-added packet being obtained by adding, to the failure notification packet, selection condition information indicating a selection condition that a second port is selected as a port to relay a packet, the second port having received the failure notification packet through the another switch. And, the processing device performs a path control of a packet based on selection condition information extracted from the selection-condition-added packet received.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: January 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kazuki Hyoudou, Yukihiro Nakagawa
  • Publication number: 20190280980
    Abstract: An information processing apparatus includes a plurality of offload devices each of which offloads and executes a relay process of a virtual switch, each of the plurality of offload devices including a memory that stores port conversion information, the port conversion information associating virtual port identifiers for identifying virtual ports before and after a virtual port to which a virtual machine executed by the information processing apparatus is connected is moved between the offload devices, and a processor coupled to the memory and that converts an input virtual port identifier for identifying an input virtual port into which a packet is input based on the port conversion information, searches an output virtual port identifier for identifying an output virtual port of the packet by using the converted input virtual port identifier, and converts the searched output virtual port identifier based on the port conversion information.
    Type: Application
    Filed: February 14, 2019
    Publication date: September 12, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Kazuki Hyoudou
  • Patent number: 10333817
    Abstract: A non-transitory computer-readable storage medium that stores a determination program that causes a communication device to execute a process including transmitting a check packet to the communication destination device, when the communication device receives a first response packet, determining whether or not header information of a second response packet is included in data of the first response packet, a communication path corresponding to the first response packet and a communication path corresponding to the second response packet being different each other, and determining that a failure occurs in the communication path corresponding to the second response packet when the header information of a second response packet is included in data of the first response packet and when the communication device does not receive the second response packet within a predetermined time from transmitting the check packet.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: June 25, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kazuki Hyoudou, Osamu Shiraki, Jun Tanaka
  • Publication number: 20190132252
    Abstract: A communication control device includes one or more memories configured to store log information indicating an input port through which a packet included in one of flows are inputted, an output port through which the packet is outputted, and time related to input of the packet, and one or more processors coupled to the one or more memories and the one or more processors configured to, on the basis of the log information, perform generation of relation information indicating relations among the flows, and when a first port is in a congested state, identify, in accordance with the relation information, an original flow on which a first flow is based, the first flow regarding a first packet included in an output queue of the first port.
    Type: Application
    Filed: October 2, 2018
    Publication date: May 2, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Kazuki Hyoudou
  • Publication number: 20180307520
    Abstract: A non-transitory computer-readable recording medium storing a program that causes a computer including a first-processor in which a first-thread is executed at a first-node having a first-buffer and a communication device and a second-processor in which a second-thread is executed at a second-node having a second-buffer, the first-thread includes setting an output-destination of the communication device to the second-buffer with respect to a flow addressed to a virtual machine executed in the second-processor, notifying the second-processor of a switch notification information of the setting the output-destination of the communication device to the second-buffer, and transferring a packet stored in the first-buffer to the second-processor, and the second-thread includes receiving the switching notification, suspending temporarily a reception-process of the second-buffer for the flow, transferring the packet transferred by the first-processor to the virtual machine, and resuming the reception-process of the se
    Type: Application
    Filed: April 19, 2018
    Publication date: October 25, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Kazuki Hyoudou
  • Patent number: 9960955
    Abstract: An information processing system includes a switching device group including a plurality of switching devices that include a switching device as a root node and switching devices as leaf nodes and are connected in a tree topology. The switching device includes: a controller that, when a failure that occurs in a communication path connected to the root node side of the switching device is detected, writes identification information indicating the communication path from which the failure is detected to a flow table which stores the identification information and output destination port information so as to be associated with each other, thereby switching a plurality of communication paths; and a notification unit that, when a failure that occurs in a communication path connected to the leaf node side of the switching device is detected, notifies another switching device connected to the switching device of a position where the failure occurs.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: May 1, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Yukihiro Nakagawa, Kazuki Hyoudou
  • Publication number: 20180048553
    Abstract: A non-transitory computer-readable storage medium that stores a determination program that causes a communication device to execute a process including transmitting a check packet to the communication destination device, when the communication device receives a first response packet, determining whether or not header information of a second response packet is included in data of the first response packet, a communication path corresponding to the first response packet and a communication path corresponding to the second response packet being different each other, and determining that a failure occurs in the communication path corresponding to the second response packet when the header information of a second response packet is included in data of the first response packet and when the communication device does not receive the second response packet within a predetermined time from transmitting the check packet.
    Type: Application
    Filed: August 3, 2017
    Publication date: February 15, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Kazuki Hyoudou, OSAMU SHIRAKI, Jun Tanaka
  • Patent number: 9847940
    Abstract: A control method executed by a packet processing device, the control method includes receiving, by a first processor, a received packet; identifying first processing execution information corresponding to the received packet, from among a plurality of first processing execution information, by referring to the first memory, based on packet identification information included in the received packet; and transmitting processing specification information included in the identified first processing execution information together with the received packet, to a second processor, when the processing specification information included in the identified first processing execution information specifies processing by the second processor; receiving, by the second processor, the processing specification information included in the identified first processing execution information and the received packet; and executing the processing for the received packet in accordance with second processing execution information specif
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: December 19, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kazuki Hyoudou, Takeshi Shimizu
  • Patent number: 9794147
    Abstract: A network switch, includes: a port configured to receive a packet from one of a first information processing device and a second information processing device: a processor configured to process the packet, wherein the processor performs operations of: extracting first information which is used for creating a request packet requesting a response of a first virtual machine executed by the first information processing device from the packet which is transmitted by the first virtual machine to a second virtual machine executed by the second information processing device; creating the request packet using the first information; transmitting the request packet to the first virtual machine; and determining an operation state of the first virtual machine based on if a response packet for the request packet is received from the first virtual machine.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: October 17, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kazuki Hyoudou, Yukihiro Nakagawa, Takeshi Shimizu
  • Patent number: 9774532
    Abstract: In an information processing system including a plurality of information processing apparatuses, a first information processing apparatus includes a first memory to store a first destination information table in which destination information and specific destination information are associated, and a first processing circuit to calculate a hash value based on destination information included in a first packet, to search the first destination information table, to select a second information processing apparatus based on the hash value, to generate a second packet by adding the hash value and specifying information, to transmit the second packet to the second information processing apparatus. The second information processing apparatus includes a second memory to store a second destination information table and a second processing circuit to receive the second packet, and to transmit to a destination represented by the specific destination information a third packet converted the second packet.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 26, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kazuki Hyoudou, Takeshi Shimizu
  • Publication number: 20170222925
    Abstract: A control method executed by a packet processing device, the control method includes receiving, by a first processor, a received packet; identifying first processing execution information corresponding to the received packet, from among a plurality of first processing execution information, by referring to the first memory, based on packet identification information included in the received packet; and transmitting processing specification information included in the identified first processing execution information together with the received packet, to a second processor, when the processing specification information included in the identified first processing execution information specifies processing by the second processor; receiving, by the second processor, the processing specification information included in the identified first processing execution information and the received packet; and executing the processing for the received packet in accordance with second processing execution information specif
    Type: Application
    Filed: April 19, 2017
    Publication date: August 3, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Kazuki HYOUDOU, Takeshi Shimizu
  • Patent number: 9699097
    Abstract: A network system includes a transmitting/receiving apparatus, a plurality of switches, and a network control apparatus. The switch includes a first packet transmission control unit and a second packet transmission control unit. The network system includes a first packet transmission control area according to the first packet transmission control unit, and a second packet transmission control area according to the second packet transmission control unit. A switch in the first packet transmission control area includes a first storage unit which stores a plurality of pieces of first rule information informed from the network control apparatus, applies a mask to a predetermined position of header information of an input packet according to the number of the plurality of pieces of first rule information, and controls the input packet according to the first rule information selected from the first storage unit based on the header information after masking.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: July 4, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kazuki Hyoudou, Yukihiro Nakagawa