Abstract: The whole of a semiconductor integrated circuit operating in synchronism with a clock signal, is divided into a plurality of circuit blocks in units of a function, and different clock signals are supplied to the circuit blocks, respectively. Each of the circuit blocks is so constructed as to minimize the clock skew, by taking into consideration the size of clock buffers and the balance in load of the clock buffers. A data signal between two circuit blocks of the circuit blocks is transferred through a queue which is controlled to fetch the data in response to the clock signal supplied to the circuit block at the input side of the queue and to output the fetched data in response to the clock signal supplied to the circuit block at the output side of the queue.

Abstract: An airbag system for a front passenger's seat of the top-mount type according to the invention is arranged in an instrument panel below a windshield. The front passenger's seat airbag system is constructed to include a door, a case and an airbag. The door is arranged on the upper face of the instrument panel. The case houses and holds the airbag in a folded state. The airbag, as housed in the case, is expanded by injecting an inflating gas into a gas inlet port so that the airbag protrudes to open the door and inflate towards the rear side of a vehicle along the windshield. The airbag is equipped with a commutator cloth arranged to cover the gas inlet port. This commutator cloth is arranged to close the two sides in the transverse direction of the vehicle and to open the two sides in the longitudinal direction of the vehicle. This front passenger's seat airbag system reduces the expansion rate of the airbag towards the rear of the vehicle.

Abstract: The present invention provides a byte-switching arithmetic unit comprising at least three stages, each of which has a plurality of two-input selectors operable in a predetermined minimum bit width unit, the byte-switching arithmetic unit having two inputs of a predetermined input bit width, wherein a first stage has a first number of first stage two-input selectors where the first number corresponds to a quotient of a division to the predetermined input bit width by the predetermined minimum bit width unit, wherein a second stage has a second number of second stage two-input selectors where the second number corresponds to a half of the first number so that the second stage two-input selectors receive a half of outputs from the first stage two-input selectors, and wherein a third stage has a third number of third stage two-input selectors where the third number also corresponds to the half of the first number so that the third stage two-input selectors receive both a half of outputs from the second stage two-

Abstract: An alternate route to improved multimedia performance without replacing the central processor unit (CPU) is presented, through the utilization of general-purpose components available in a computer. The method relies on the use of integrated circuit memory boards having a data port for directly inputting encoded image signals from an I/O device into the memory. An on-board decoder provided on the IC memory is used to decode the variable-length encoded input signals. This approach enalbes to reduce the computational load on the CPU so that the usual bottleneck which is the slow process of data exchange between the CPU and the memory boards is eliminated. The CPU directly accesses the processed image data in the memory and displays the final image on the monitor. This route to increasing the image processing speed of a computer has considerable merits because it is low cost and is readily applicable to mass-produced IC memories with only a few additional fabrication steps.

Abstract: In a microprocessor having conditional execution instructions, an execution halt circuit incorporated in an instruction decoder temporarily halts the execution of a current instruction according to the operation result of a preceding instruction in a program. When a conditional execution decision circuit judges to cancel the execution of the preceding instruction, the conditional execution decision circuit cancels a start signal indicating to initiate the operation of the preceding instruction. Furthermore, the conditional execution decision section or circuit judges whether a conditional data stored in a general purpose flag is equal to a condition stored in an execution conditional field, and bypass control sections control use of bypasses and data passes for data transfer operation according to the decision result of the conditional execution decision section.

Abstract: A multiplying method with a negative/positive symmetrical round-off function and circuitry therefor are disclosed. When a product is positive, a value having a (logical) ONE at the uppermost one of bits to be rounded and ZEROs at the lower bits is rounded up. When a product is negative, a value having a (logical) ONE at the uppermost one of bits to be rounded and ZEROs at the lower bits is rounded down. This rounds off the product such that a mean accumulative error when the product is positive and a mean cumulative error when it is negative cancel each other. When a product is positive, a correction term having a ONE at the uppermost one of the bits to be rounded and ZEROs at the lower bits is applied to a subproduct adder and an adder. For a negative product, the correction term has a ZERO at the above uppermost bit and ZEROs at the lower bits.

Abstract: A phase locked loop in a LSI comprises a phase comparator, a low-pass filter, a voltage controlled oscillator and a frequency divider, and receives an input clock signal to output an internal clock signal obtained by multiplication of the input clock signal. The output of the low-pass filter is supplied through a voltage follower from an external pin toward outside the integrated circuit. The output voltage of the low-pass filter is evaluated during a test mode for evaluating the function of the phase locked loop without affecting the characteristics of the phase locked loop.

Abstract: A liquid oil and fat ingredient or others are carried by pores of a porous carrier composed of porous starch grain obtained by reacting an enzyme having raw starch digestive activity onto the starch. With starch being used as porous carrier, the powder preparation according to the present invention is not harmful to the human body, it can be supplied continuously in great volumes, manufactured cheaply without difficult processing, and moreover, being completely biodegradable, this powder preparation does not cause any environmental problems. It can be used in various industrial fields.

Abstract: A pipelined data processing arrangement which is subject to an instruction interrupt is disclosed. The pipelined arrangment is provided with a plurality of stages each of which has a temporary storage. In order to increase an actual time for executing instructions in the pipelined arrangement, the temporary storages which exhibit large delay are replaced by dynamic latches each having a smaller delay time without adversely affecting the operation of the pipelined arrangement.

Abstract: In a semiconductor device including a plurality of semiconductor cells each of which has a diffusion area, a first metal layer, and a connecting portion, the first metal layer overlies whole of the diffusion area while the connecting portion covers almost whole of the diffusion area. The semiconductor device further includes a second metal layer, and first and second power supply lines. The second metal layer has an interconnecting area positioned above the semiconductor cells and an overlapping area overlapping on the first metal layer. Each of the first and the second power supply lines consists of the overlapping area. The semiconductor cells are electrically connected to each other by a third metal layer and the interconnecting area of the second metal layer.

Abstract: In a counter circuit, an n-bit input signal is stored into a register in response to a clock pulse and then dumped out of the register in response to a subsequent clock pulse and divided into a lower m-bit component and a higher (n-m)-bit component. The lower m-bit component is summed with a 1 to produce a summed m-bit component and a carry if the lower m-bit component is all 1's. The higher (n-m)-bit component is summed with a 1 to produce a summed (n-m)-bit component. In the absence of a carry, the divided (n-m)-bit component is selected and in the presence of the carry the summed (n-m)-bit component is selected. Either of the selected (n-m)-bit components is combined with the summed m-bit component to produce a summed n-bit signal which is stored back into the register.

Abstract: A plurality of horn switches are provided between a steering wheel body and a horn pad provided above the steering wheel body. Each of the horn switches includes a spacer having an insulating property, a horn spring which is connected to a positive electrode of a horn operating circuit and urges the horn pad upwardly, a tongue connected to a negative electrode of the horn operating circuit, and a shearable shoulder bolt. The horn spring and the tongue are mounted on the spacer. The spacer has a tubular portion having an enlarged portion formed on an outer peripheral surface thereof at a distal end thereof. The tubular portion is retained in a retaining hole in the steering wheel body. The shoulder bolt is inserted into the tubular portion from an end thereof opposite to the horn pad, and is screw-mounted to the horn pad.

Abstract: Ground lines 2 are disposed so as to sandwich a power supply line 1. A gate oxide film 3 and a gate 4 are formed below the power supply line 1. An n-type area 8 is formed adjacent to the end of the gate oxide film to set the ground potential thereto. A p-type area 9 is formed at most of the remaining part below the ground line to make it contact the substrate. Since the potential of the gate equals that of the power source, an inversion layer is formed below the oxide film, where the ground potential results through the n-type area. By sandwiching the gate oxide film between the gate and the inversion layer, a capacitor is formed.

Abstract: A pipelined data processing arrangement which is subject to an instruction interrupt is disclosed. The pipelined arrangement is provided with a plurality of stages each of which has a temporary storage. In order to increase an actual time for executing instructions in the pipelined arrangement, the temporary storages which exhibit large delay are replaced by dynamic latches each having a smaller delay time without adversely affecting the operation of the pipelined arrangement.

Abstract: The present invention comprises a novel strain of Lactobacillus johnsonni FERM BP-2680, a lactic acid bacteria preparation using the Lactobacillus johnsonni FERM BP-2680, and a process of manufacturing the lactic acid bacteria preparation. The process includes the steps of inoculating the Lactobacillus johnsonni FERM BP-2680 into a medium containing fermentable sugar as a major carbon source, cultivating and proliferating under cultivation conditions adapted to anaerobes or facultative anaerobes, and further isolating the Lactobacillus johnsonni from the medium and drying the isolated Lactobacillus johnsonni with a protective agent to produce the lactic acid bacteria preparation. Optionally a bulking agent may be added to control cell concentration of the preparation. The preparation containing Lactobacillus johnsonni FERM BP-2680 is used to suppress harmful bacteria in the digestive tract of mammals.

Abstract: In an overflow detection circuit for A+B operation, an inverter outputs a value V.sub.B ' comprising inverted bits of a numeric part of an addend B. A comparator receives as an input a numeric part V.sub.A of an augend A and an output V.sub.B ' of the inverter, and responsive thereto outputs a signal C indicating whether or not V.sub.A >V.sub.B ' is given. Sign parts S.sub.A and S.sub.B of A and B and the output C of the comparator are inputted into the a decoder and an overflow signal "0" is outputted. The decoder is a circuit which outputs "1" when S.sub.A and S.sub.B are "0" and V.sub.A (V.sub.A >V.sub.B ') is large and when S.sub.A and S.sub.B are "1" and V.sub.A is small (VA=V.sub.B '), and output "0" in other cases. If the comparator is a circuit for determining V.sub.A .gtoreq.V.sub.B ', the overflow of A+B+1 can be detected. Thus, the overflow of the result of operation can be detected earlier than an adder and a substracter output the results.

Abstract: A ball joint has a ball seat fitted in a through hole of a socket. A recessed part of the socket has the same diameter as a receiving part of the ball seat. An attaching part of a dust cover is clamped into the recess formed by the recessed part and the receiving part to seal the interior of the ball joint from the entry of moisture and dirt, and to provide lateral support to the ball seat. A double-ended version is disclosed wherein attaching parts of two dust covers seal and provide lateral support to opposed ends of the ball seat.

Abstract: A ball joint wherein a ball seat having a closed side is insertewd between an inner surface of a housing and an outer surface of a ball portion of a ball stud, the ball seat being formed of a hard synthetic resin, and having an annular flange after on the closed side of the ball seat engaged with an opened edge at one side of the housing, an annular flange engaged with an opened edge at the other side of the housing, and an annular recess provided on the inner circumferential side of the annular flange on the closed side of the ball seat and enabling the same annular flange.

Abstract: The sweetner prepared by adding palatinose to sucrose is a low-cariogenic since palatinose is not only low cariogenic in itself, but also inhibits the formation of insoluble glucan from sucrose in an oral cavity.Since the sweetner is almost same as sucrose in quality of sweetness, dissolvability in a mouth, palatability, etc., and further is low-cariogenic when it is used in foods, it is suitable as sweetner. In addition, since the sweetner is usually crystalline or powdery, it is easy to handle.

Abstract: A magnetic particulate comprising gelatin, water-soluble polysaccharide, sodium polymetaphosphate and ferromagnetic substance, which is used as a carrier for immobilization of biological proteins such as antigens, antibodies or enzymes, and a process of producing the magnetic particulate.