Patents by Inventor Kazumasa Yanagisawa
Kazumasa Yanagisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6381671Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: GrantFiled: June 29, 1999Date of Patent: April 30, 2002Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20020012272Abstract: A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to flow a channel current according to the threshold voltage of the non-volatile memory element.Type: ApplicationFiled: March 9, 2001Publication date: January 31, 2002Inventors: Shoji Shukuri, Kazumasa Yanagisawa
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Publication number: 20020009834Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.Type: ApplicationFiled: September 28, 2001Publication date: January 24, 2002Applicant: Hitachi, Ltd.Inventors: Takao Watanabe, Kazushige Ayukawa, Ryo Fujita, Kazumasa Yanagisawa
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Patent number: 6335898Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.Type: GrantFiled: March 16, 2001Date of Patent: January 1, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Engineering CorporationInventors: Takao Watanabe, Kazushige Ayukawa, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka
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Patent number: 6314044Abstract: A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.Type: GrantFiled: June 15, 2000Date of Patent: November 6, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Toshio Sasaki, Yuji Tanaka, Kazumasa Yanagisawa, Hitoshi Tanaka, Jun Sato, Takashi Miyamoto, Mariko Ohtsuka, Satoru Nakanishi, Kazushige Ayukawa, Takao Watanabe
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Publication number: 20010028581Abstract: A dynamic RAM includes sense amplifiers each formed of a latch circuit consisting of MOSFETs of a first and second conductivity types with the application of a first and second voltages to the sources thereof, respectively, and having a pair of input/output nodes corresponding to a first bit line pair which is connected with a number of dynamic memory cells, and further includes pairs of switching MOSFETs of the first conductivity type which connect selectively an input/output node pair of the latch circuits to a pair of second bit lines provided commonly to a plurality of the first bit line pair in response to the reception of the select signal. The switching MOSFETs have their threshold voltage set smaller in terms of absolute value than the threshold voltage of the MOSFETs of the first conductivity type of the latch circuits, and the select signal has its level of turning off the switching MOSFETs set greater in terms of absolute value than the first voltage with respect to the second voltage.Type: ApplicationFiled: March 30, 2001Publication date: October 11, 2001Applicant: Hitachi, Ltd.Inventors: Kazumasa Yanagisawa, Toshio Sasaki, Satoru Nakanishi, Yoshihiko Yasu
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Patent number: 6301184Abstract: A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.Type: GrantFiled: January 11, 2000Date of Patent: October 9, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Toshio Sasaki, Yoshihiko Yasu, Kazumasa Yanagisawa, Yuji Tanaka, Toshiaki Takahira, Yasuto Igarashi, Mariko Ohtsuka, Yasunobu Aoki
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Publication number: 20010019499Abstract: To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, address for salvaging defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit, thereby, a special process is not needed in forming the nonvolatile memory element, that is, the nonvolatile memory element can be formed in a process of forming CMOS device and apparatus of laser beam for programming is not needed since the programming is carried out in testing, time necessary for programming can be shortened and therefore, testing cost can be reduced.Type: ApplicationFiled: February 12, 2001Publication date: September 6, 2001Inventors: Koichiro Ishibashi, Shoji Shukuri, Kazumasa Yanagisawa, Junichi Nishimoto, Masanao Yamaoka, Masakazu Aoki
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Publication number: 20010014051Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.Type: ApplicationFiled: March 16, 2001Publication date: August 16, 2001Applicant: Hitachi, Ltd.Inventors: Takao Watanabe, Kazushiqe Ayukawa, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka
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Publication number: 20010009551Abstract: Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.Type: ApplicationFiled: March 5, 2001Publication date: July 26, 2001Inventors: Norihiko Moriwaki, Kenichi Sakamoto, Akihiko Takase, Akio Makimoto, Kazumasa Yanagisawa
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Patent number: 6249524Abstract: Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.Type: GrantFiled: March 19, 1998Date of Patent: June 19, 2001Assignee: Hitachi, Ltd.Inventors: Norihiko Moriwaki, Kenichi Sakamoto, Akihiko Takase, Akio Makimoto, Kazumasa Yanagisawa
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Patent number: 6246629Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.Type: GrantFiled: April 18, 2000Date of Patent: June 12, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Takao Watanabe, Kazushige Ayukawa, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka
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Patent number: 6115319Abstract: A bootstrap circuit is provided for a word line selector for setting word lines connected with dynamic memory cells at a select level corresponding to a first voltage and a nonselect level corresponding to a second voltage. The bootstrap circuit generates a bootstrap voltage which is given a difference substantially equal to the threshold voltage of address select MOSFETs with respect to the high level of bit lines connected with the memory cells, and feeds the bootstrap voltage to the selected word lines. The bootstrap circuit is activated in synchronism with a clock signal at a timing corresponding to an action mode designated by a command in an SDRAM before a precharge action, thereby changing the select level of the word lines from the first voltage to the bootstrap voltage.Type: GrantFiled: February 13, 1998Date of Patent: September 5, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Yoshitaka Kinoshita, Kenji Nishimoto, Kazumasa Yanagisawa, Hitoshi Tanaka
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Patent number: 6108264Abstract: An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.Type: GrantFiled: January 19, 1999Date of Patent: August 22, 2000Assignee: Hitachi, Ltd.Inventors: Yasushi Takahashi, Takashi Shinoda, Masamichi Ishihara, Tetsu Udagawa, Kazumasa Yanagisawa
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Patent number: 6097663Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.Type: GrantFiled: October 6, 1999Date of Patent: August 1, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering CorporationInventors: Takao Watanabe, Kazushige Ayukawa, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka
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Patent number: 6091660Abstract: A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.Type: GrantFiled: August 18, 1999Date of Patent: July 18, 2000Assignees: Hitachi, Ltd., Hitachi USLI Systems Co., Ltd.Inventors: Toshio Sasaki, Yuji Tanaka, Kazumasa Yanagisawa, Hitoshi Tanaka, Jun Sato, Takashi Miyamoto, Mariko Ohtsuka, Satoru Nakanishi, Kazushige Ayukawa, Takao Watanabe
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Patent number: 6069834Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.Type: GrantFiled: March 7, 1997Date of Patent: May 30, 2000Assignees: Hitachi, Ltd., Hitachi Ulsi Engineering CorporationInventors: Takao Watanabe, Kazushige Ayukawa, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka
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Patent number: 5995439Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.Type: GrantFiled: November 10, 1998Date of Patent: November 30, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Engineering CorporationInventors: Takao Watanabe, Kazushige Ayukawa, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka
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Patent number: 5978305Abstract: A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.Type: GrantFiled: October 2, 1998Date of Patent: November 2, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Toshio Sasaki, Yuji Tanaka, Kazumasa Yanagisawa, Hitoshi Tanaka, Jun Sato, Takashi Miyamoto, Mariko Ohtsuka, Satoru Nakanishi, Kazushige Ayukawa, Takao Watanabe
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Patent number: 5862095Abstract: An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.Type: GrantFiled: October 31, 1997Date of Patent: January 19, 1999Assignee: Hitachi, Ltd.Inventors: Yasushi Takahashi, Takashi Shinoda, Masamichi Ishihara, Tetsu Udagawa, Kazumasa Yanagisawa