Patents by Inventor Kazumasa Yanagisawa

Kazumasa Yanagisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memories
    Patent number: 6949782
    Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: September 27, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Bryan Atwood, Kazuo Yano, Tomoyuki Ishii, Taro Osabe, Kazumasa Yanagisawa, Takeshi Sakata
  • Semiconductor integrated circuit device
    Publication number: 20050152186
    Abstract: To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
    Type: Application
    Filed: March 7, 2005
    Publication date: July 14, 2005
    Inventors: Koichiro Ishibashi, Shoji Shukuri, Kazumasa Yanagisawa, Junichi Nishimoto, Masanao Yamaoka, Masakazu Aoki
  • Semiconductor integrated circuit device
    Publication number: 20050146953
    Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
    Type: Application
    Filed: January 24, 2005
    Publication date: July 7, 2005
    Inventors: Hiroyuki Mizuno, Yusuke Kanno, Kazumasa Yanagisawa, Yoshihiko Yasu, Nobuhiro Oodaira
  • Semiconductor integrated circuit device
    Patent number: 6911683
    Abstract: A semiconductor integrated circuit device has a semiconductor substrate with a plurality of pads disposed over a main surface of the substrate along one side thereof. A plurality of input/output cells are disposed corresponding to the plural pads over the main surface of the substrate. An internal circuit forming section is disposed over the main surface of the substrate. Power supply wirings for the internal circuit supply potentials to the internal circuit forming section. The plural input/output cells include signal cells and power supply cells for internal circuit respectively. Signal pads are disposed corresponding to the signal cells and electrically connected the signal cells. Power supply pads for the internal circuit are respectively disposed corresponding to the power supply cells and electrically connected to the power supply cells and the power supply wirings.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: June 28, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Satoru Konishi, Mitsuaki Katagiri, Kazumasa Yanagisawa
  • Semiconductor device, a method of manufacturing the same and storage media
    Patent number: 6897496
    Abstract: Outside-cell wiring that extends the upper part of a macro cell to the direction of X axis is composed of the wiring layer of the upper layer than a terminal for a signal of the macro cell and this terminal is formed to extend in the direction of Y axis (direction that intersects the direction of X axis) so that the outside-cell wiring can be secured for a plurality of wiring channels. The macro cell and the outside-cell wiring are connected via this signal terminal.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: May 24, 2005
    Assignees: Hitachi, Ltd., Renesas Technology Corporation
    Inventors: Toshio Yamada, Kazumasa Yanagisawa, Yoshihiro Shinozaki, Hidetomo Aoyagi
  • Semiconductor integrated circuit device
    Patent number: 6894944
    Abstract: To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: May 17, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Koichiro Ishibashi, Shoji Shukuri, Kazumasa Yanagisawa, Junichi Nishimoto, Masanao Yamaoka, Masakazu Aoki
  • Semiconductor integrated circuit and data processing system
    Publication number: 20050099876
    Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
    Type: Application
    Filed: December 14, 2004
    Publication date: May 12, 2005
    Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
  • Semiconductor integrated circuit device
    Patent number: 6888395
    Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: May 3, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Hiroyuki Mizuno, Yusuke Kanno, Kazumasa Yanagisawa, Yoshihiko Yasu, Nobuhiro Oodaira
  • Semiconductor integrated circuit and data processing system
    Patent number: 6847578
    Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: January 25, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
  • Semiconductor device
    Publication number: 20040257142
    Abstract: A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.
    Type: Application
    Filed: January 15, 2004
    Publication date: December 23, 2004
    Applicant: Renesas Technology Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Kazumasa Yanagisawa
  • Semiconductor device
    Publication number: 20040223389
    Abstract: A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to cause a channel current to flow according to the threshold voltage of the non-volatile memory element.
    Type: Application
    Filed: June 9, 2004
    Publication date: November 11, 2004
    Inventors: Shoji Shukuri, Kazumasa Yanagisawa
  • Semiconductor device
    Patent number: 6791881
    Abstract: A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to cause a channel current to flow according to the threshold voltage of the non-volatile memory element.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: September 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Shoji Shukuri, Kazumasa Yanagisawa
  • Semiconductor memories
    Patent number: 6787835
    Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two- and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: September 7, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Bryan Atwood, Kazuo Yano, Tomoyuki Ishii, Taro Osabe, Kazumasa Yanagisawa, Takeshi Sakata
  • Semiconductor memories
    Publication number: 20040164326
    Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.
    Type: Application
    Filed: March 2, 2004
    Publication date: August 26, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Bryan Atwood, Kazuo Yano, Tomoyuki Ishii, Taro Osabe, Kazumasa Yanagisawa, Takeshi Sakata
  • Semiconductor memory device
    Publication number: 20040125681
    Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ss1 of the driver MOS transistors in the memory cells.
    Type: Application
    Filed: December 12, 2003
    Publication date: July 1, 2004
    Inventors: Masanao Yamaoka, Kenichi Osada, Kazumasa Yanagisawa
  • Semiconductor integrated circuit and data processing system
    Publication number: 20040114451
    Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
    Type: Application
    Filed: December 9, 2003
    Publication date: June 17, 2004
    Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
  • Semiconductor integrated circuit device
    Publication number: 20040075157
    Abstract: A semiconductor integrated circuit device comprises a semiconductor substrate squared in plane surface, a plurality of pads disposed over a main surface of the semiconductor substrate along one side of the semiconductor substrate, a plurality of input/output cells disposed corresponding to the plural pads over the main surface of the semiconductor substrate, an internal circuit forming section disposed over the main surface of the semiconductor substrate and inner than the plural input/output cells, and power supply wirings for internal circuit, for supplying potentials to the internal circuit forming section, which are respectively disposed inner than the plural input/output cells. The plural input/output cells include signal cells and power supply cells for internal circuit respectively.
    Type: Application
    Filed: September 10, 2003
    Publication date: April 22, 2004
    Inventors: Satoru Konishi, Mitsuaki Katagiri, Kazumasa Yanagisawa
  • Semiconductor integrated circuit device
    Publication number: 20040065961
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a Cu wiring is not smaller than about 0.9 &mgr;m and smaller than about 1.44 &mgr;m and the width of another Cu wiring and the diameter of a plug are about 0.18 &mgr;m, there are arranged two or more plugs which connect the Cu wirings and another Cu wirings electrically with each other on the Cu wiring.
    Type: Application
    Filed: June 20, 2003
    Publication date: April 8, 2004
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni
  • Semiconductor integrated circuit and data processing system
    Patent number: 6708249
    Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: March 16, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
  • Semiconductor device
    Patent number: 6700429
    Abstract: A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: March 2, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Kazumasa Yanagisawa