Patents by Inventor Kazumi Inoh

Kazumi Inoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5886395
    Abstract: To obtain both the highest possible maximum operating frequency f.sub.max and early voltage V.sub.A, a semiconductor device provided with a bipolar transistor including a collector region, a base region formed on the collector region, an emitter region formed in contact with the base region, a base leading electrode connected to the base region, and an emitter electrode connected to the emitter region, is characterized in that a ratio Q.sub.B /N.sub.c of base Gunmel number Q.sub.B to impurity concentration N.sub.C of the collector region of the bipolar transistor lies within a range from 0.2.times.10.sup.-3 cm to 2.5.times..sup.-3 cm.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: March 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Katsumata, Chihiro Yoshino, Kazumi Inoh
  • Patent number: 5866446
    Abstract: To enable a high speed operation and to increase the current gain, the disclosed a method of manufacturing a semiconductor device, comprising the steps of: forming a first semiconductor layer with a first-conductivity type in a semiconductor substrate; forming a second semiconductor layer with a second-conductivity type different from the first-conductivity type on the first semiconductor layer; insulation separating the formed second semiconductor layer into a first semiconductor region and a second semiconductor region by an insulating film; changing the second semiconductor region to the first-conductivity type; forming a pattern of an insulating film or a photoresist film having a hole at a partial area of the first semiconductor region of the semiconductor substrate; and implanting first-conductivity type impurities and second-conductivity type impurities at the first semiconductor region, respectively by use of the formed pattern as a mask, to form a first-conductivity type impurity region contacting wi
    Type: Grant
    Filed: March 11, 1997
    Date of Patent: February 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazumi Inoh
  • Patent number: 5620908
    Abstract: A method of manufacturing a semiconductor device including selectively forming an element-isolating insulating layer on a surface of a semiconductor substrate to define active regions; forming a first insulating layer and removing respective portions thereof on surfaces of a second conductive type active region and a first active region of a first conductive type; oxidizing to form a gate oxide layer; forming and patterning a conductive layer to form a gate electrodes of MOS transistors and a base-extracting electrode of a bipolar transistor; forming an opening, in the base-extracting electrode, and a side wall insulating layer on an inner wall of the opening; removing first and second portions of the insulating layer to form an overhung portion; epitaxially growing a second conductive type semiconductor layer using the base-extracting electrode and active region of the first conductive type as a seed crystal; and selectively forming a first conductive type semiconductor layer that is to become an emitter tha
    Type: Grant
    Filed: September 19, 1995
    Date of Patent: April 15, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumi Inoh, Yasuhiro Katsumata, Satoshi Matsuda, Chihiro Yoshino