Patents by Inventor Kazunari Michii
Kazunari Michii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7348191Abstract: A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the corresponding solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.Type: GrantFiled: June 23, 2006Date of Patent: March 25, 2008Assignee: Renesas Technology Corp.Inventors: Kazunari Michii, Naoyuki Shinonaga, Shinji Semba
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Patent number: 7166490Abstract: A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the closest solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.Type: GrantFiled: January 6, 2003Date of Patent: January 23, 2007Assignee: Renesas Technology Corp.Inventors: Kazunari Michii, Naoyuki Shinonaga, Shinji Semba
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Publication number: 20060240596Abstract: A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the corresponding solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.Type: ApplicationFiled: June 23, 2006Publication date: October 26, 2006Applicant: Renesas Technology Corp.Inventors: Kazunari Michii, Naoyuki Shinonaga, Shinji Semba
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Patent number: 6858938Abstract: A semiconductor device includes a substrate; an external electrode terminal for electrically connecting to an external electrode; a first semiconductor chip provided above the substrate, having a plurality of electrode pads disposed on a major surface thereof; a second semiconductor chip provided above the first semiconductor chip, having a plurality of electrode pads disposed on a major surface thereof; and connection lines for connecting the electrode pads to the external electrode. A part of the major surface of the first semiconductor chip faces a part of the surface opposite to the major surface of the second semiconductor chip; and the first semiconductor chip is shifted from the second semiconductor chip, so that the second semiconductor chip does not overlap the electrode pads of the first semiconductor chip.Type: GrantFiled: February 11, 2003Date of Patent: February 22, 2005Assignee: Renesas Technology Corp.Inventor: Kazunari Michii
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Patent number: 6836004Abstract: A lead frame comprises a plurality of frame assemblies. Each framework assembly includes a framework, a suspension lead, a die pad, a plurality of inner leads and outer leads, a first tie bar and a second tie bar, and a lead support. The plurality of framework assemblies are disposed alongside of one another in a direction perpendicular to a direction in which the plurality of outer leads extend. A distance between close-set outer leads in each two neighboring frameworks is substantially n times a pitch of the plurality of outer leads in each framework, wherein n is an integer.Type: GrantFiled: January 15, 2003Date of Patent: December 28, 2004Assignee: Renesas Technology Corp.Inventors: Kazunari Michii, Naoyuki Shinonaga, Shinji Semba
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Patent number: 6836007Abstract: A semiconductor package includes an upper substrate having an opening portion, a solder ball for connection between substrates arranged on the lower side of the upper substrate, a lower substrate arranged on the further lower side and having an opening portion, a solder ball for external connection connected on the lower surface of the lower substrate, and a semiconductor chip affixed on each substrate. The semiconductor chip is electrically connected to the solder ball through the opening portion of each substrate. The solder ball for connection between substrates is electrically connected to the solder ball for external connection.Type: GrantFiled: March 10, 2003Date of Patent: December 28, 2004Assignee: Renesas Technology Corp.Inventors: Kazunari Michii, Jun Shibata
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Patent number: 6798056Abstract: A semiconductor module includes a substrate having a pad electrode on a surface, a lower layer semiconductor package mounted on the substrate, and an upper layer semiconductor package mounted on the substrate while arranged in a position substantially overlying the former. The pad electrodes connected to the leads of these semiconductor packages are arranged alternately. The lead has a dambar residual portion. An inner surface of a lead downward portion of the upper layer semiconductor package is positioned outside an outer surface of a lead downward portion of the lower layer semiconductor package.Type: GrantFiled: August 30, 2002Date of Patent: September 28, 2004Assignee: Renesas Technology Corp.Inventors: Tetsuya Matsuura, Yasushi Kasatani, Kazunari Michii
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Publication number: 20040159925Abstract: In a semiconductor device, a first semiconductor including a substrate, and a semiconductor chip disposed on the major surface of the substrate and sealed with a resin; a wiring board; spacers disposed between the wiring board and the substrate; and a second semiconductor. At this time, the second semiconductor is electrically connected to the wiring board and disposed in the space formed by the wiring board, the substrate, and the spacer. The spacer is disposed so as to the first semiconductor to the wiring board electrically.Type: ApplicationFiled: July 29, 2003Publication date: August 19, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Tetsuya Matsuura, Kazunari Michii, Jun Shibata, Koji Bando
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Patent number: 6737733Abstract: In an LOC semiconductor device, a semiconductor chip is fixed on a die pad through a die pad material. A lead including an internal lead extending to the vicinity of a pad provided to the semiconductor chip is put in place. A tape member is placed at positions corresponding to four corners of the semiconductor chip between the internal lead and the semiconductor chip. The tape member is bonded and fixed only to the internal lead but it is not bonded or fixed to the semiconductor chip and merely contacts the surface of the semiconductor chip.Type: GrantFiled: May 4, 2001Date of Patent: May 18, 2004Assignee: Renesas Technology Corp.Inventors: Kazuyuki Misumi, Kazunari Michii, Yoshihiro Hirata
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Publication number: 20040061211Abstract: A semiconductor package includes an upper substrate having an opening portion, a solder ball for connection between substrates arranged on the lower side of the upper substrate, a lower substrate arranged on the further lower side and having an opening portion, a solder ball for external connection connected on the lower surface of the lower substrate, and a semiconductor chip affixed on each substrate. The semiconductor chip is electrically connected to the solder ball through the opening portion of each substrate. The solder ball for connection between substrates is electrically connected to the solder ball for external connection.Type: ApplicationFiled: March 10, 2003Publication date: April 1, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kazunari Michii, Jun Shibata
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Publication number: 20040026789Abstract: A semiconductor device includes a substrate; an external electrode terminal for electrically connecting to an external electrode; a first semiconductor chip provided above the substrate, having a plurality of electrode pads disposed on a major surface thereof; a second semiconductor chip provided above the first semiconductor chip, having a plurality of electrode pads disposed on a major surface thereof; and connection lines for connecting the electrode pads to the external electrode. A part of the major surface of the first semiconductor chip faces a part of the surface opposite to the major surface of the second semiconductor chip; and the first semiconductor chip is shifted from the second semiconductor chip, so that the second semiconductor chip does not overlap the electrode pads of the first semiconductor chip.Type: ApplicationFiled: February 11, 2003Publication date: February 12, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Kazunari Michii
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Publication number: 20040018663Abstract: A lead frame comprises a plurality of frame assemblies. Each framework assembly includes a framework, a suspension lead, a die pad, a plurality of inner leads and outer leads, a first tie bar and a second tie bar, and a lead support. The plurality of framework assemblies are disposed alongside of one another in a direction perpendicular to a direction in which the plurality of outer leads extend. A distance between close-set outer leads in each two neighboring frameworks is substantially n times a pitch of the plurality of outer leads in each framework, wherein n is an integer.Type: ApplicationFiled: January 15, 2003Publication date: January 29, 2004Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Kazunari Michii, Naoyuki Shinonaga, Shinji Semba
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Publication number: 20040007783Abstract: A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the closest solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.Type: ApplicationFiled: January 6, 2003Publication date: January 15, 2004Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Kazunari Michii, Naoyuki Shinonaga, Shinji Semba
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Patent number: 6670701Abstract: A semiconductor module achieving higher density of the semiconductor module itself as well as of being disposed in an area-efficient manner relative to another electronic component, such as a mother board and the like. The semiconductor module includes a mounting substrate having, on an underside, a solder ball for connecting to an interconnection of a mother board and semiconductor packages mounted in multiple layers on the top side of the mounting substrate and connected to electrodes on the mounting substrate.Type: GrantFiled: December 4, 2001Date of Patent: December 30, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuya Matsuura, Yasushi Kasatani, Kazunari Michii, Hajime Maeda
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Publication number: 20030174481Abstract: A semiconductor module includes a substrate having a pad electrode on a surface, a lower layer semiconductor package mounted on the substrate, and an upper layer semiconductor package mounted on the substrate while arranged in a position substantially overlying the former. The pad electrodes connected to the leads of these semiconductor packages are arranged alternately. The lead has a dambar residual portion. An inner surface of a lead downward portion of the upper layer semiconductor package is positioned outside an outer surface of a lead downward portion of the lower layer semiconductor package.Type: ApplicationFiled: August 30, 2002Publication date: September 18, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuya Matsuura, Yasushi Kasatani, Kazunari Michii
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Patent number: 6614101Abstract: A plastic packaged semiconductor device is constructed by sealing, with a sealing plastic, a semiconductor chip which has an electrode pad arranged in a central portion of an upper surface, a die pad to which the semiconductor chip is die-bonded, bonding wires which are connected to the electrode pad, and inner leads which are arranged in close vicinity of the die pad and have tip portions having upper flat surfaces which are positioned at a level equal to or higher than the upper surface of the semiconductor chip and to which the bonding wires are connected. Accordingly, the small thin plastic packaged semiconductor device in which the bonding wires do never come into contact with the edge of the semiconductor chip can be achieved.Type: GrantFiled: May 26, 2000Date of Patent: September 2, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuyuki Misumi, Kazunari Michii, Manabu Horita
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Patent number: 6583511Abstract: A laminated semiconductor chip assembly fabricated by fixing back surfaces of first and second semiconductor chips, respectively having principal surfaces and back surfaces, to each other. Each of the principal surfaces of the laminated semiconductor chip assembly is fixed to a corresponding surface of a lead frame. A standing linear portion of a metallic wire on a ball bond side is pulled parallel to a side surface of the semiconductor chip in its thickness direction and a side surface of the inner lead in its thickness direction, and subjected to wire bonding. The formed semiconductor chip assembly is covered by a sealing resin so that an outer lead protrudes from the sealing resin. Thus, the semiconductor device can be made thin, cost can be reduced, and quality can be improved to increase capacities of electronic equipment.Type: GrantFiled: July 13, 2001Date of Patent: June 24, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazunari Michii, Tatsuhiko Akiyama
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Patent number: 6552418Abstract: A back surface of a semiconductor chip having an integrated circuit for a 64M DRAM is die-bonded to a first surface of a die pad provided virtually in the middle of the thickness of encapsulations resin, an electrode thereof and an upper surface of the tip end of an inner lead are wire bonded with a metal wire. A back surface of a semiconductor chip having an integrated circuit for a flash memory is die-bonded to a second surface of the die pad, and an electrode arranged at an end on the longer side and a back surface of an inner lead root portion are wire-bonded with a metal wire. Then, these elements are integrally encapsulated with encapsulation resin. Thus, a thin, compact, reliable and inexpensive lead frame with large integration capacity and a resin-encapsulated semiconductor device using the lead frame produced by integrally resin-encapsulating a plurality of semiconductor chips including at least a center pad type semiconductor chip are provided.Type: GrantFiled: March 1, 2001Date of Patent: April 22, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuyuki Misumi, Kazunari Michii
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Patent number: 6545366Abstract: In order to reduce the thickness of a semiconductor device and double its capacity, two center pad semiconductor chips stacked one on the other, back to back, are fixed to one face of a wiring substrate. The difference in the length of routing between external lands and fingers is minimized, and each of the center pads and corresponding fingers are connected via metal wires having a high conductivity. The main face of a first center pad semiconductor chip is fixed to the wiring substrate that has first and second wired faces and a through opening. The back face of the first semiconductor chip and the back face of a second semiconductor chip are fixed to each other using a bonding material. The pads on each semiconductor chip are connected to corresponding fingers on the wiring substrate via metal wires. One face of the wiring substrate is sealed with a sealing resin, and on the other face, an area in the vicinity of the through opening is sealed.Type: GrantFiled: June 25, 2001Date of Patent: April 8, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazunari Michii, Tatsuhiko Akiyama
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Patent number: D475981Type: GrantFiled: August 16, 2002Date of Patent: June 17, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Kazunari Michii