Abstract: According to an embodiment, a semiconductor device includes an error corrector, a read controller, and a majority processor. The error corrector is configured to perform error correction on data read from a storage, and output the number of errors contained in the data when errors cannot be corrected by the error correction. The read controller is configured to read pieces of data from a first address in the storage according to respective read conditions, select, from the read conditions, a read condition corresponding to a smallest of the numbers of errors obtained by the error correction performed on the pieces of data corresponding to the respective read conditions, and perform reading from the first address multiple times according to the selected read condition. The majority processor is configured to perform a majority process between a plurality of pieces of data obtained by the multiple times of reading.

Abstract: According to an embodiment, a semiconductor device includes an error corrector, a read controller, and a majority processor. The error corrector is configured to perform error correction on data read from a storage, and output the number of errors contained in the data when errors cannot be corrected by the error correction. The read controller is configured to read pieces of data from a first address in the storage according to respective read conditions, select, from the read conditions, a read condition corresponding to a smallest of the numbers of errors obtained by the error correction performed on the pieces of data corresponding to the respective read conditions, and perform reading from the first address multiple times according to the selected read condition. The majority processor is configured to perform a majority process between a plurality of pieces of data obtained by the multiple times of reading.

Abstract: A semiconductor memory device which includes multi-bit memory cells that store multi-bit data and memory cells that store data of fewer bits then that of the multi-bit data. Thus, the semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h?n) data is stored in a memory MLC of a first region MLB, and i-bit (i<h) data is stored in a memory SLC of a second region SLB. If the number of rewritings in the memory cells of the second region SLB reaches a prescribed value, the i-bit data is stored in the memory of the first region MLB rather than the memory cells of the second region SLB.

Abstract: Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h?n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array and a control circuit. The distribution state of the threshold voltages of the memory cells is monitored by the read operation, the distribution state of the threshold voltages of the memory cells after the soft erasure is monitored, and an erase voltage is set based on the monitored results. Thus, the erase voltage can be precisely set without depending on the threshold voltage distribution of the memory cell before the erasure.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array and a controller. The memory cell array includes first, second, and third memory cells each of which stores k-bit data (where k is a natural number not smaller than 1). The first and second memory cells are adjacent to each other, and the second and third memory cells are adjacent to each other. Data is stored into the memory cells in an order of the first, second, and third memory cells. When reading data from the second memory cells, the controller reads data from the first and third memory cells, and changes read conditions for the second memory cell in accordance with the read data.

Abstract: A semiconductor memory device which includes multi-bit memory cells that store multi-bit data and memory cells that store data of fewer bits then that of the multi-bit data. Thus, the semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h?n) data is stored in a memory MLC of a first region MLB, and i-bit (i<h) data is stored in a memory SLC of a second region SLB. If the number of rewritings in the memory cells of the second region SLB reaches a prescribed value, the i-bit data is stored in the memory of the first region MLB rather than the memory cells of the second region SLB.

Abstract: A semiconductor memory device, in which a multi-bit region including multi-bit memory cells that store data of two or more bits and a region including memory cells that store data of bits that are less than the bits of the data stored in the multi-bit memory cells are installed, is provided, which can perform a high-speed writing and lengthen the life span of the product without increasing the storage capacity of the region of the memory cells storing the data of bits that are less than the bits of the data in the multi-bit memory cells. The semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h?n) data is stored in a memory MLC of a first region MLB, and i-bit (i<h) data is stored in a memory SLC of a second region SLB.

Abstract: Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h?n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells.

Abstract: Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h?n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array and a control circuit. The distribution state of the threshold voltages of the memory cells is monitored by the read operation, the distribution state of the threshold voltages of the memory cells after the soft erasure is monitored, and an erase voltage is set based on the monitored results. Thus, the erase voltage can be precisely set without depending on the threshold voltage distribution of the memory cell before the erasure.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array and a controller. The memory cell array includes first, second, and third memory cells each of which stores k-bit data (where k is a natural number not smaller than 1). The first and second memory cells are adjacent to each other, and the second and third memory cells are adjacent to each other. Data is stored into the memory cells in an order of the first, second, and third memory cells. When reading data from the second memory cells, the controller reads data from the first and third memory cells, and changes read conditions for the second memory cell in accordance with the read data.

Abstract: A semiconductor memory device, in which a multi-bit region including multi-bit memory cells that store data of two or more bits and a region including memory cells that store data of bits that are less than the bits of the data stored in the multi-bit memory cells are installed, is provided, which can perform a high-speed writing and lengthen the life span of the product without increasing the storage capacity of the region of the memory cells storing the data of bits that are less than the bits of the data in the multi-bit memory cells. The semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h?n) data is stored in a memory MLC of a first region MLB, and i-bit (i<h) data is stored in a memory SLC of a second region SLB.

Abstract: In a memory cell array, a plurality of memory cells which store data in the form of n values (n is a natural number which is not smaller than 2) which are in first and second to nth states are arranged in a matrix form. Before a write operation of storing data in a first memory cell in the memory cell array, when at least one second memory cell which is adjacent to the first memory cell is in the first state and does not reach a first threshold voltage, a control circuit performs a write operation in the second memory cell up to the first threshold voltage.

Abstract: Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h?n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells.

Abstract: A number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

Abstract: A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell storing data defined by threshold voltage thereof, wherein the memory cell array includes first and second areas; the first area stores multi-value data written with plural write steps; and the second area stores binary data defined by first and second logic states, threshold levels of which are controlled through the plural write steps adapted to the multi-value data write.

Abstract: The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

Abstract: A nonvolatile semiconductor memory includes a memory cell array, a page buffer that is connected to the memory cell array and retains program verification results of a write-in operation of repeating data write-in and program verification, a bit scan circuit that is connected to the page buffer and determines whether or not the number of fail bits is equal to or less than number of reference bits based on the program verification results retained in the page buffer, a register that is connected to the bit scan circuit and retains determination results of the bit scan circuit, and a sequencer that controls the write-in operation and an operating sequence of the bit scan circuit and terminates the write-in operation while leaving the number of fail bits in response to the results temporarily stored in the register.

Abstract: In a memory cell array, a plurality of memory cells which store data in the form of n values (n is a natural number which is not smaller than 2) which are in first and second to nth states are arranged in a matrix form. Before a write operation of storing data in a first memory cell in the memory cell array, when at least one second memory cell which is adjacent to the first memory cell is in the first state and does not reach a first threshold voltage, a control circuit performs a write operation in the second memory cell up to the first threshold voltage.