Abstract: A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell storing data defined by threshold voltage thereof, wherein the memory cell array includes first and second areas; the first area stores multi-value data written with plural write steps; and the second area stores binary data defined by first and second logic states, threshold levels of which are controlled through the plural write steps adapted to the multi-value data write.

Abstract: A number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

Abstract: A nonvolatile semiconductor memory includes a memory ell array, a page buffer that is connected to the memory cell array and retains program verification results of a write-in operation of repeating data write-in and program verification, a bit scan circuit that is connected to the page buffer and determines whether or not the number of fail bits is equal to or less than number of reference bits based on the program verification results retained in the page buffer, a register that is connected to the bit scan circuit and retains determination results of the bit scan circuit, and a sequencer that controls the write-in operation and an operating sequence of the bit scan circuit and terminates the write-in operation while leaving the number of fail bits in response to the results temporarily stored in the register.

Abstract: The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

Abstract: A plurality of projections each are arranged on a substrate at an interval smaller than a predetermined distance and made of an insulating material. A semiconductor chip is arranged over a substrate on which these projections are formed. A mounting material is provided between the substrate and the semiconductor chip to achieve a bond therebetween.

Abstract: A mask ROM for storing multi-value data has a memory cell comprising a primary conductive region formed by a first conductive type semiconductor, a source region formed in the primary conductive region by a second conductive type semiconductor, a drain region formed in the primary conductive region by the second conductive type semiconductor, a channel region adjacently formed with the source region and the drain region, a gate insulation layer formed on the channel region, and a gate electrode formed on the gate insulation layer, wherein the channel region or the gate electrode is divided into a plurality of parts, each divided part having a different layer thickness from the other or a different transmissivity for ion injection, so as to form a ROM.

Abstract: A mask ROM for storing multi-value data has a memory cell comprising a primary conductive region formed by a first conductive type semiconductor, a source region formed in the primary conductive region by a second conductive type semiconductor, a drain region formed in the primary conductive region by the second conductive type semiconductor, a channel region adjacently formed with the source region and the drain region, a gate insulation layer formed on the channel region, and a gate electrode formed on the gate insulation layer, wherein the channel region or the gate electrode is divided into a plurality of parts, each divided part having a different layer thickness from the other or a different transmissivity for ion injection, so as to form a ROM.

Abstract: A memory cell is formed in the main surface area of a semiconductor substrate. An inter-level insulation film is formed on the substrate to cover the memory cell. An opening is formed in the inter-level insulation film to reach the memory cell. An internal wiring layer is electrically connected to the memory cell via the opening. A protection film is formed on the inter-level insulation film to cover the internal wiring layer. The protection film is formed of a material containing at least silicon and oxygen and the refractive index thereof is set within a range of 1.48 to 1.65.

Abstract: A memory cell array is formed of a plurality of nonvolatile memory cell transistors arranged in a matrix form. The patterns of the control gate electrode and the source region of each memory cell transistor are formed in parallel and the pattern of the erasing gate electrode is formed to intersect the source region and control gate electrode patterns. A field oxide film is formed in an intersecting portion between the source region and the erasing gate electrode.

Abstract: A method of manufacturing a semiconductor device having the steps of: forming a plurality of gate electrodes on a semiconductor substrate; forming an insulating film on every second gate electrode of the plurality of gate electrodes; coating resist on the whole surface of the semiconductor device to form a first resist film; patterning the first resist film and removing a predetermined area to form a second resist film, the end face of the second resist film being aligned with the surface of the gate electrode without the insulating film; implanting impurity ions, using the second resist film as a mask, at an acceleration voltage allowing to stop the implanted ions near to the surface of the semiconductor substrate under the gate electrode with the insulating film, of those gate electrodes not covered with the second resist film; removing the second resist film and coating resist on the whole surface of the semiconductor device to form a third resist film; patterning the third resist film and removing a prede

Abstract: A semiconductor memory device containing a number of memory cells each having a floating gate, an erase gate, and a control gate. In a data erasure mode, electrons are discharged from the floating gate into the erase gate. In the semiconductor memory device, an impurity concentration in at least a region of the floating gate overlapping with the erase gate is lower than that of the erase gate.

Abstract: The present invention provides a manufacturing method for a semiconductor storage device, in which data are written by implanting impurity ions onto a channel area of a memory cell transistor, which comprises the steps of: a step for forming a gate electrode using a high melting point metal over the surface of a semiconductor substrate, and for forming an oxide film on the surface of the gate electrode; a step for forming a film on the area for forming a data confirmation pattern; and a step for forming the data confirmation pattern on the film in performing etching in the film at a high selection ratio for the above-mentioned oxide film with a mask to be used for ion implantation for ROM data.

Abstract: This invention relates to a method of manufacturing a read only semiconductor memory device such as a NAND type ROM, etc. In this device, a plurality of memory cells are connected in series. These memory cells are such that first memory cells each having a first gate electrode made up at a process step and second memory cells each having a second gate electrode made up at a different process step are arranged one after another. According to whether or not an impurity of a second conductivity type is introduced into the surface portion of a first conductivity type impurity layer just under the first and second gate electrodes, respective memory cells store one logical value of binary data.